![](http://datasheet.mmic.net.cn/20000/S1C7XXXF00E199_datasheet_1390192/S1C7XXXF00E199_11.png)
1 SUMMARY
S1C17 FAMILY S1C17 CORE MANUAL
EPSON
1-1
1 Summary
The S1C17 Core is a Seiko Epson original 16-bit RISC-type processor.
It features low power consumption, high-speed operation with a maximum 60 MHz to 90 MHz clock, large address
space up to 16M bytes addressable, main instructions executable in one clock cycle, and a small sized design. The
S1C17 Core is suitable for embedded applications that do not need a lot of data processing power like the S1C33
Cores the high-end processors, such as controllers and sequencers for which an eight-bit CPU is commonly used.
The S1C17 Core incorporates a coprocessor interface allowing implementation of additional computing features.
Furthermore, Seiko Epson provides a software development environment similar to the S1C33 Family that includes
an IDE work bench, a C compiler, a serial ICE and a debugger, for supporting the developer to develop application
software.
1.1 Features
Processor type
Seiko Epson original 16-bit RISC processor
0.35–0.15 m low power CMOS process technology
Operating-clock frequency
90 MHz maximum (depending on the processor model and process technology)
Instruction set
Code length:
16-bit fixed length
Number of instructions:
111 basic instructions (184 including variations)
Execution cycle:
Main instructions executed in one cycles
Extended immediate instructions: Immediate extended up to 24 bits
Compact and fast instruction set optimized for development in C language
Register set
Eight 24-bit general-purpose registers
Two 24-bit special registers
One 8-bit special register
Memory space and bus
Up to 16M bytes of memory space (24-bit address)
Harvard architecture using separated instruction bus (16 bits) and data bus (32 bits)
Interrupts
Reset, NMI, and 32 external interrupts supported
Address misaligned interrupt
Debug interrupt
Direct branching from vector table to interrupt handler routine
Programmable software interrupts with a vector number specified (all vector numbers specifiable)
Power saving
HALT (halt instruction)
SLEEP (slp instruction)
Coprocessor interface
ALU instructions can be enhanced