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7 DETAILS OF INSTRUCTIONS
S1C17 FAMILY S1C17 CORE MANUAL
EPSON
7-37
jpr
sign10
jpr.d sign10
Function
Unconditional PC relative jump
Standard)
pc
← pc + 2 + sign10 × 2
Extension 1) pc
← pc + 2 + sign24
Extension 2) Unusable
Code
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0 0 0 1 0 0
sign10
jpr
|
0 0 0 1 0 1
sign10
jpr.d
|
Flag
IL IE
C
V
Z
N
– – – – – –
|
Mode
Signed PC relative
CLK
jpr
Three cycles
jpr.d
Two cycles
Description (1) Standard
jpr
sign10
; = "jp sign11", sign7 = sign11(8:1), sign11(0)=0
Doubles the signed 10-bit immediate sign10 and adds it to the PC (PC + 2). The program flow
branches to the address. The sign10 specifies a word address in 16-bit units.
The sign10 (
×2) allows branches within the range of PC - 1,022 to PC + 1,024.
(2) Extension 1
ext
imm13
; = sign24(23:11)
jpr
sign10
; = "jpr sign24", sign10 = sign24(10:1), sign24(0)=0
The ext instruction extends the displacement to be added to the PC (PC + 2) into 24 bits using
its 13-bit immediate imm13.
The sign24 allows branches within the range of PC - 8,388,606 to PC + 8,388608.
(3) Delayed branch (d bit (bit 10) = 1)
jpr.d
sign10
For the jpr.d instruction, the next instruction becomes a delayed slot instruction. A delayed
slot instruction is executed before the program branches. Interrupts are masked in intervals
between the jpr.d instruction and the next instruction, so no interrupts occur.
Example
ext
0x20
jpr
0x00 ; Jumps to the address specified by pc + 2 + 0x10000.
Caution
When the jpr.d instruction (delayed branch) is used, be careful to ensure that the next instruction
is limited to those that can be used as a delayed slot instruction. If any other instruction is executed,
the program may operate indeterminately. For the usable instructions, refer to the instruction list in
the Appendix.