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参数资料
| 型号： | S1T0567X01-D0B0 |
| 元件分类： | 信令电路 |
| 英文描述： | TELECOM, TONE DECODER CIRCUIT, PDIP8 |
| 封装： | 0.300 INCH, DIP-8 |
| 文件页数： | 6/8页 |
| 文件大小： | 561K |
| 代理商： | S1T0567X01-D0B0 |
S1T0567
TONE DECODER
6
Input (Pin 3)
The input signal is applied to pin 3 through a coupling capacitor. This terminal is internally biased at a DC level 2
volts above ground, and has an input impedance level of approximately 20k
.
Timing Resistor R1 and Capacitor C1 (Pins 5 and 6)
The center frequency of the decoder is set by resistor R1 between pins 5 and 6, and capacitor C1 from pin 6 to
ground, as shown in Figure 1.
Pin 5 is the oscillator squarewave output which has a magnitude of approximately VCC - 1.4V and an average DC
level of VCC/2. A 1 k load may be driven from this point. The voltage at pin 6 is an exponential triangle waveform
with a peak-to-peak amplitude of 1 volt and an average DC level of VCC/2. Only high impedance loads should be
connected to pin 6 to avoid disturbing the temperature stability or duty cycle of the oscillator.
Logic Output (Pin 8)
Terminal 8 provides a binary logic output when an input signal is present within the pass-band of the decoder. The
logic output is an uncommitted, base-collector power transistor capable of switching high current loads. The current
level at the output is determined by an external load resistor RL, connected from pin 8 to the positive supply.
When an inband signal is present, the output transistor at pin 8 saturates with a collector voltage less than 1 volt
(typically 0.6V) at full rated current of 100mA. If large output voltage swings are needed, RL can be connected to a
supply voltage, V+, higher than the VCC supply. For safe operation, V+ ≤ 20 volts.
OPERATING INSTRUCTIONS
SELECTION OF EXTERNAL COMPONENTS
A typical connection diagram for S1T0567 is shown in Figure 1. For most applications, the following procedure will
be sufficient for determination of the external components R1, C1, C2, and C3.
1. R1 and C1 should be selected for the desired center frequency by the expression fO =1/R1C1. For optimum
temperature stability, R1 should be selected so that 2 K and the R1C1 product have sufficient stability over the
projected operating temperature range.
2. C2 is a low-pass capacitor.
If the input amplitude variation is known, the required fOC2 product can be found to give the desired bandwidth.
Capacitor C2 connected from pin 2 to ground serves as a single pole, low-pass filter for the PLL portion of the
S1T0567 solely by the fOC2 product.
3. Capacitor C3 sets the band edge of the low-pass filter which attenuates frequencies outside of the detection
band and thereby eliminates spurious outputs. If C3 is too small, frequencies adjacent to the detection band may
switch the output stage off and on at the beat frequency, or the output may pulse off and on during the turn-on
transient. A typical minimum value of C3 is 2 C2.
Conversely, if C3 is too large, turn-on and turn-off of the output stage will be delayed until the voltage across C3
passes the threshold value.
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