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参数资料
| 型号： | S1T0567X01-D0B0 |
| 元件分类： | 信令电路 |
| 英文描述： | TELECOM, TONE DECODER CIRCUIT, PDIP8 |
| 封装： | 0.300 INCH, DIP-8 |
| 文件页数： | 7/8页 |
| 文件大小： | 561K |
| 代理商： | S1T0567X01-D0B0 |
TONE DECODER
S1T
0567
7
PRINCIPLE OF OPERATION
The S1T0567 is a frequency selective tone decoder system based on the phase-locked loop (PLL) principle. The
system is comprised of a phase-locked loop, a quadrature AM detector, a voltage comparator, and an output logic
driver. The four sections are internally interconnected as shown in block diagram.
When an input tone is present within the pass-band of the circuit, the PLL synchronizes or “locks” on the input
signal. The quadrature detector serves as a lock indicator : when the PLL is locked on an input signal, the DC
voltage at the output of the detector is shifted. This DC level shift is then converted to an output logic pulse by the
amplifier and logic driver. The logic driver is a “bare collector” transistor stage capable of switching 100mA loads.
The logic output at pin 8 is normally in a “high” state, until a tone that is within the capture range of the decoder is
present at the input. When the decoder is locked on an input signal, the logic output at pin 8 goes to a “low” state.
The center frequency of the detector is set by the free-running frequency of the current-controlled oscillator in the
PLL.
This free-running frequency, fO, is determined by the selection of R1 and C1 connected to pins 5 and 6, as shown in
Figure 1. The detection bandwidth is determined by the size of the PLL filter capacitor, C2; and the output response
speed is controlled by the output filter capacitor, C3.
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