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参数资料
| 型号： | S29AL008D90MFI011 |
| 厂商： | SPANSION LLC |
| 元件分类： | PROM |
| 英文描述： | 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
| 中文描述： | 512K X 16 FLASH 3V PROM, 90 ns, PDSO44 |
| 封装： | LEAD FREE, MO-180AAA, SOP-44 |
| 文件页数： | 8/52页 |
| 文件大小： | 2004K |
| 代理商： | S29AL008D90MFI011 |
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16
S29AL008D
S29AL008D_00_A11 February 27, 2009
Da ta
Sh e e t
7.7
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading array data. When the
RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in
progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse.
The device also resets the internal state machine to reading array data. The operation that was interrupted
should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3 V, the device
draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS±0.3 V, the standby current is
greater.
The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firmware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a 0 (busy) until the
internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The
system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is
asserted when a program or erase operation is not executing (RY/BY# pin is 1), the reset operation is
completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the
RESET# pin returns to VIH.
Refer to AC Characteristics on page 36 for RESET# parameters and to Figure 15.2 on page 37 for the timing
diagram.
7.8
Output Disable Mode
When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high
impedance state.
Note
Address range is A18:A-1 in byte mode and A18:A0 in word mode. See Word/Byte Configuration on page 14.
Table 7.2 S29AL008D Top Boot Block Sector Addresses
Sector
A18
A17
A16
A15
A14
A13
A12
Sector Size
(Kbytes/
Kwords)
Address Range (in hexadecimal)
(x8)
Address Range
(x16)
Address Range
SA0
0
X
64/32
00000h–0FFFFh
00000h–07FFFh
SA1
0
1
X
64/32
10000h–1FFFFh
08000h–0FFFFh
SA2
0
1
0
X
64/32
20000h–2FFFFh
10000h–17FFFh
SA3
0
1
X
64/32
30000h–3FFFFh
18000h–1FFFFh
SA4
0
1
0
X
64/32
40000h–4FFFFh
20000h–27FFFh
SA5
0
1
0
1
X
64/32
50000h–5FFFFh
28000h–2FFFFh
SA6
0
1
0
X
64/32
60000h–6FFFFh
30000h–37FFFh
SA7
0
1
X
64/32
70000h–7FFFFh
38000h–3FFFFh
SA8
1
0
X
64/32
80000h–8FFFFh
40000h–47FFFh
SA9
1
0
1
X
64/32
90000h–9FFFFh
48000h–4FFFFh
SA10
1
0
1
0
X
64/32
A0000h–AFFFFh
50000h–57FFFh
SA11
1
0
1
X
64/32
B0000h–BFFFFh
58000h–5FFFFh
SA12
1
0
X
64/32
C0000h–CFFFFh
60000h–67FFFh
SA13
1
0
1
X
64/32
D0000h–DFFFFh
68000h–6FFFFh
SA14
1
0
X
64/32
E0000h–EFFFFh
70000h–77FFFh
SA15
1
0
X
32/16
F0000h–F7FFFh
78000h–7BFFFh
SA16
1
11100
8/4
F8000h–F9FFFh
7C000h–7CFFFh
SA17
1
11101
8/4
FA000h–FBFFFh
7D000h–7DFFFh
SA18
1
1111
X
16/8
FC000h–FFFFFh
7E000h–7FFFFh
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相关代理商/技术参数 |
参数描述 |
|---|---|
| S29AL008D90MFI012 | 制造商:SPANSION 制造商全称:SPANSION 功能描述:8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
| S29AL008D90MFI013 | 制造商:SPANSION 制造商全称:SPANSION 功能描述:8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
| S29AL008D90MFI020 | 制造商:SPANSION 制造商全称:SPANSION 功能描述:8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
| S29AL008D90MFI021 | 制造商:SPANSION 制造商全称:SPANSION 功能描述:8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
| S29AL008D90MFI022 | 制造商:SPANSION 制造商全称:SPANSION 功能描述:8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
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