参数资料
型号: S29WS064N0PBAW010
厂商: SPANSION LLC
元件分类: PROM
英文描述: 256/128/64 MEGABIT CMOS 1.8 VOLT ONLY SIMULTANEOUS READ/WRITE BURST MODE FLASH MEMORY
中文描述: 4M X 16 FLASH 1.8V PROM, 70 ns, PBGA80
封装: 9 X 7 MM, LEAD FREE, PLASTIC, FBGA-80
文件页数: 18/95页
文件大小: 1745K
代理商: S29WS064N0PBAW010
October 29, 2004 S29WSxxxN_00_F0
25
Pre l i m i n a r y
Table 7.15. Configuration Register
Reading the Configuration Table. The configuration register can be read with a four-cycle
command sequence. See Table 12.1 for sequence details. Once the data has been read from
the configuration register, a software reset command is required to set the device into the
correct state.
7.4 Autoselect
The Autoselect mode provides manufacturer and device identification, and sector protection
verification, through identifier codes output from the internal register (separate from the
memory array) on DQ15-DQ0. This mode is primarily intended for programming equipment
to automatically match a device to be programmed with its corresponding programming al-
gorithm. The Autoselect codes can also be accessed in-system. When verifying sector
protection, the sector address must appear on the appropriate highest order address bits (see
Tables 7.17 to 7.16). The remaining address bits are don't care. When all necessary bits have
been set as required, the programming equipment may then read the corresponding identifier
code on DQ15-DQ0. The Autoselect codes can also be accessed in-system through the com-
mand register. Note that if a Bank Address (BA) on the four uppermost address bits is
asserted during the third write cycle of the Autoselect command, the host system can read
Autoselect data from that bank and then immediately read array data from the other bank,
without exiting the Autoselect mode.
CR Bit
Function
Settings (Binary)
CR15
Set Device Read Mode
0 = Synchronous Read (Burst Mode) Enabled
1 = Asynchronous Read Mode (default) Enabled
CR14
Boundary Crossing
0 = No extra boundary crossing latency
1 = With extra boundary crossing latency (default)
Must be set to “1” at higher operating frequencies. See Tables 7.10–7.13.
CR13
CR12
CR11
Programmable
Wait State
000 = Data valid on 2nd active CLK edge after addresses latched
001 = Data valid on 3rd active CLK edge after addresses latched
010 = Data valid on 4th active CLK edge after addresses latched (recommended for 54 MHz)
011 = Data valid on 5th active CLK edge after addresses latched (recommended for 66 MHz)
100 = Data valid on 6th active CLK edge after addresses latched (recommended for 80 MHz)
101 = Data valid on 7th active CLK edge after addresses latched (default)
110 = Reserved
111 = Reserved
Inserts wait states before initial data is available. Setting greater number of wait states before initial data
reduces latency after initial data. See Tables 7.6–7.13.
CR10
RDY Polarity
0 = RDY signal active low
1 = RDY signal active high (default)
CR9
Reserved
1 = default
CR8
RDY
0 = RDY active one clock cycle before data
1 = RDY active with data (default)
When CR13-CR11 are set to 000, RDY will be active with data regardless of CR8 setting.
CR7
Reserved
1 = default
CR6
Reserved
1 = default
CR5
Reserved
0 = default
CR4
Reserved
0 = default
CR3
Burst Wrap Around
0 = No Wrap Around Burst
1 = Wrap Around Burst (default)
CR2
CR1
CR0
Burst Length
000 = Continuous (default)
010 = 8-Word Linear Burst
011 = 16-Word Linear Burst
100 = 32-Word Linear Burst
(All other bit settings are reserved)
Note: Configuration Register will be in the default state upon power-up or hardware reset.
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