S3C3410X RISC MICROPROCESSOR
SYSTEM MANAGER
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SYSTEM MANAGER
OVERVIEW
The S3C3410X System Manager has the following functionality:
Arbitrate the bus usage requests from several master blocks, based on a fixed priority.
Generate the necessary memory control signals for external memory access. For example, if a master block
such as DMA or the CPU generates an address which corresponds to a DRAM bank, the DRAM controller
inside System Manager should generate the necessary DRAM control signals (nRAS, nCAS, and so on).
Support only the big-endian mode. The access to the internal register or the external memory should be done
based on the big-endian mode.
SYSTEM MANAGER REGISTER
The S3C3410X microcontroller has the SFRs, Special Function Register Set, to keep the system control
information of system manager, cache, DMA, UART, and so on. The SFRs have the SMRs, System Manager
Register Set, to configure the external memory map as well as the access-related option for SDRAM, DRAM,
SRAM, ROM and extra-I/O control.
By utilizing the SMR, user can specify the memory type, external bus width, access cycles, necessary control
signal timings(nRAS, nCAS, and so on), location of memory bank, and each memory bank size. The SMR can
provide(or accept) the information of control signals, address, and data which are required by external devices
during normal system operation. There are eleven registers to control memory bank (ROM, SRAM,
DRAM/SDRAM), extra-device control and DRAM refresh.
The S3C3410X can provide up to 128M bytes of address space and each bank can provide up to 16M bytes
memory space because each bank can have 24 address pins and 8-bit/16-bit data width.
The S3C3410X can also support two external I/O banks. These I/O banks are mapped into the SFR region. The
two external I/O bank can give the smart interface between S3C3410X and external I/O device, which will
improve the cost, PCB size, and reliability of system.