UNIFIED CACHE & INTERNAL SRAM
S3C3410X RISC MICROPROCESSOR
5-6
CACHE FLUSHING
The cache content as well as Tag at the specific line can be accessed by S/W. In S3C3410X, the memory array
of set 0 is mapped to the address of 0x10000000 – 0x100007ff, which is 2KB size. Similarly, the memory array of
set 1 is mapped to the address of 0x10800000 – 0x108007ff, which is also 2KB size. The Tag array is also
mapped to the address of 0x11000000 – 0x110001ff, which is 512B size. As we explained in previous chapter,
the width of Tag data is total 36-bit, which consists of 2bit CS, 17/16-bit Tag data for 2KB/4KB for set 0, and
17/16-bit Tag data for 2KB/4KB for set 1. In detail, the 16-bit Tag data(Tag[15:0]) of set 1 and 16-bit Tag
data(Tag[15:0]) of set 1 is mapped to the address of 0x11000000. The CS field of the Tag is mapped to the
address of 0x11000004. In this case, CS[1] and CS[0] are corresponding to the data bus of D[31] and D[30]. If
user specify the 2KB cache size, lower 16-bit Tag data of set 1 and lower 16-bit Tag data of set 0 is mapped to
the address of 0x11000000. The remained CS field, upper Tag bit of set 1 and upper Tag bit of set 0 are mapped
to the address of 0x11000004. In this case, CS[1], CS[0], Tag[16] for set 1, and Tag[16] for set 0 are
corresponding to the data bus of D[31], D[30], D[29], and D[28]. The next line will be corresponding to the
address of 0x11000008, 0x11000010, and so on. The memory allocation table of the Tag RAM and Set 0, 1
cache memory is as follows:
Item
Address
Comment
Set 0
0x10000000 – 0x100007ff
2KB
Set 1
0x10800000 – 0x108007ff
2KB
Tag RAM
0x11000000 – 0x110001ff
512B
NOTE: Cache flushing must be executed only in the cache disable mode.
NON-CACHE AREA CONTROL BIT
The S3C3410X can support the 128MB addressing range and it means that the internal address A[26:0] are only
effective even if the CPU can generate the A[31:0] of the internal address. If the S/W generate the address
beyond this range, the cache controller and the memory controller will treat this address as special case. The
reality is as follow. The cache controller accepts the address of A[27:0] and determine whether this access should
be cached, or not when A[27]=0. In other word, the access should be cached if the A[26:0] is corresponding to the
cacheable region and should not be cached if the A[26:0] is corresponding to the non-cacheable region. If A[27] =
1, the cache controller treat this access as non-cacheable access even if the A[26:0] is corresponding to
cacheable or non-cacheable region. When A[27]=1 and the A[26:0] is corresponding to the cacheable region, the
cache controller should treat this access as non-cacheable access and the memory controller should execute the
memory access by using A[26:0] address. The cache controller discard the address of A[31:28] and the memory
controller also discard the address of A[31:27].