
S3FB42F
USB
23-15
IN Control Status Register
For Endpoints other than 0, separate in and out registers are available and micro-code should read the
register the endpoint has been programmed for.
Register
Address
R/W
Description
Reset Value
INCSR
0x8A
R/W
IN control status register
00h
ENDPT1CSR BIT
USB
MCU
Description
IN_PKT_RDY
R/C
R/W
When packet has been load into FIFO by MCU and ready for
transfer to the host, write '1' to this bit.
UNDERRUN
W
R/C
USB under-run error during ISO.
FORCE STALL
R/C
R/W
Force a stall handshake to the host.
ISO
R
R/W
if set, indicates an isocronous endpoint.
INTPT_ENDPT
R
R/W
if set, USB sends packet whatever data is there in the FIFO.
IN_PKT_RDY2
R/C
R
When MCU writes a '1' to bit 0,this bit is always set. It is cleared
by the USB when the data has been transferred to the host.
FIFO_FLUSH
R/C
W
The MCU sets this bit if it intends to flush the IN FIFO.
This bit is cleared by the USB when the FIFO is flushed. The MCU
is interrupted when this happens. If a token is in progress, the USB
waits until the transmissions in complete before the FIFO is
flushed.
CLR_DATA_TOGGLE
R
W
When the MCU writes a 1 to this bit, the data toggle bit is cleared.
This is a write-only.
IN_PKT_RDY: The micro controller after filling the FIFO with a IN data, set this bit. MCU should wait for this bit to be
cleared by the USB before loading next IN token. If the function receives a valid IN token, while IN PKT RDY is not
set by the micro controller then the endpt state machine issues a NAK handshake.
UNDER RUN: This bit is used to isocronous endpoints. It is set if the function times out to an IN token.
ISO: if this bit is set, the endpoint behaves as an isocronous endpoint.
FORCE_STALL: This bit is set by the micro controller. Whenever this bit is set, the function controller issues a
STALL handshake to the host. This bit may be set by the MCU for any fault condition within the function or when
host does a SET_FEATURE (ENDPOINT_STALL). It is cleared by the micro controller when it receives a
CLEAR_FEATURE (ENDPOINT_STALL) command from the host.
IN_PKT_RDY2: When MCU writes a *1* to bit 0 position, this bit always gets set and is cleared by the hardware
when all the packets have been transferred to the host.