
S3FB42F
USB
23-17
Out Control Status Register
Register
Address
R/W
Description
Reset Value
OUTCSR
0x8B
R/W
OUT control status register
00h
OUT CSR BIT
USB
MCU
Description
OUT_PKT_RDY
W
R/C
Packet received from the host is ready in the FIFO
OVERRUN
W
R/C
This is set only in ISO mode. USB sets this bit when overrun is
detected.
SEND_STALL
R/C
R/W
MCU forces a stall handshake to the host.
FORCE_STALL
W
R/C
USB sets this bit when OUT transaction ended with STALL
handshake.
This happens when:
1. Host sends more then MAXP data.
2. USB detected protocol violation.
ISO
R
R/W
if set, indicates an isocronous endpoint.
DATA_ERR
W
R/C
This is set only in ISO mode. USB sets this bit if at the time of
setting OUTPKTRDY if an error has occurred.
OUT_PKT_RDY: The GFI sets this bits, whenever it has a valid token packet in the endpt1 FIFO. The micro
controller seeing this bit set, unloads the FIFO and clears this bit by doing writing a *1* to this bit. At the time of
clearing this bit, the micro controller should also set SEND_STALL if a stall condition exists.
OVERRUN: This is used for isochronous endpoints only, if an OUT token packet is receved and the out_pkt_rdy from
the pervious transactions is not cleared, the USB discard the data and set this bit to indicate to the micro controller
that an OUT packet was lost.
SEND_STALL: This bit is set by the micro controller. Whenever this bit is set, the function controller issues a
STALL handshake to the host.
This bit may be set by the MCU for any fault condition within the function or when host does a
SET_FEATURE(ENDPOINT_STALL). It is cleared by the micro controller when it receives a
CLEAR_FEATURE(ENDPOINT_STALL) command from the host.
ISO: if this bit is set, the endpoint behaves as an isocronous endpoint.
If this bit is dear, the endpoint be haves as a bulk or interrupt endpoint.
FORCE_STALL: USB sets this bit when OUT transaction ended with STALL handshake.
This happens when:
1. Host sends more than MAXP data.
2. USB detected protocol violation.
DATA_ERR: For ISO endpoint , HW sets OUT PKT RDY even if the core has a CRC/bit stuffing error. But
DATA_ERR bit is also set in this case. If the microcode is capable of error recovery it can unload the packet, else it
can flush the FIFO, which will clear out the FIFO and reset OUT PKT RDY.