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参数资料
| 型号： | S5D0127X01-Q0R0 |
| 厂商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | MULTISTANDARD VIDEO DECODER/SCALER |
| 中文描述： | 多标准视频解码器/倍线器 |
| 文件页数： | 47/96页 |
| 文件大小： | 1509K |
| 代理商： | S5D0127X01-Q0R0 |
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ELECTRONICS
S5D0127X01 Data Sheet
MULTIMEDIA VIDEO
PAGE 47 OF 96
Modified on May/04/2000
The second byte the host sends is the base register index. The host then sends the data. The S5D0127X01
increments the index automatically after each byte of data is sent. Therefore, the host can write multiple bytes to
the slave if they are in sequential order. The host completes the transfer cycle with a STOP signal which is a LOW
to HIGH transition when the SCLK is high.
Each byte transfer consists of 9 clocks. When writing to the S5D0127X01, an acknowledge signal is asserted by
the salve device during the 9th clock.
Figure 39. IIC Data Write
A read cycle takes two START-STOP phases. The first phase is a write to the index register. The second phase is
the read from the data register.
The host initiates the first phase by sending the START signal. It then sends the slave device ID along with a 0 in
the R/W position. The index is then sent followed by the STOP signal.
The second phase also starts with the START signal. It then sends the slave device ID but with a 1 in the R/W
position to indicate data is to be read from the slave device. The host uses the SCLK to shift data out from the
S5D0127X01. A typical second phase in a read transaction is depicted in Figure 40. Auto index increment is
supported in Read mode.
Figure 40. IIC Data Read
SCLK
SDAT
device ID
index
data
data
START
STOP
ACK
ACK
ACK
SCLK
SDAT
device ID
index
START
STOP
ACK
ACK
SCLK
SDAT
device ID
data
START
STOP
NACK
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