参数资料
型号: S5D0127X01-Q0R0
厂商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: MULTISTANDARD VIDEO DECODER/SCALER
中文描述: 多标准视频解码器/倍线器
文件页数: 57/96页
文件大小: 1509K
代理商: S5D0127X01-Q0R0
ELECTRONICS
S5D0127X01 Data Sheet
MULTIMEDIA VIDEO
PAGE 57 OF 96
Modified on May/04/2000
AGC Control
Index
Mnemonic
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0x0B
AGC
AGC[7:0]
AGC[7:0]
This register is used to manually set AGC when
AGCFRZ
is set to “1”. The content in the
register is unsigned.
Chroma Demodulation Control
Index
Mnemonic
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0Dh
CDEM
OUTHIZ
FSEC
0
CIFCMP[1:0]
0
0
0
CIFCMP[1:0]
IF compensation for the chroma path.
0
No compensation.*
1
Upper chroma side band is 1 dB higher than lower side band.
2
Upper chroma side band is 3 dB higher than lower side band.
3
Upper chroma side band is 6 dB higher than lower side band.
Chroma frequency demodulation filter select for SECAM video.
0
Select SECAM chroma frequency demodulation filter if SECAM video is detected.*
1
Always use SECAM chroma frequency demodulation filter.
This is the software output three-state control bit. If this bit is set to a “1”, or the OEN pin is at a
logic LOW level, output pins can be selectively put in the high impedance state using the
additional software control bits
OENC[1:0]
.
0
This is default setting.*
1
This will enable the output pins to be three-stated regardless the state of the OEN
pin.
FSEC
OUTHIZ
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