参数资料
型号: S6A0069
元件分类: 显示控制器
英文描述: 16 X 40 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC80
封装: DIE-80
文件页数: 8/35页
文件大小: 368K
代理商: S6A0069
S6A0069
40 SEG / 16 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
16
Table 7. Instruction Table
Instruction Code
Instruction
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Description
Instruction Code
Execution time
(fsoc=270kHz)
Clear Display
0
1
Write "20H" to DDRAM. and set
DDRAM address to "00H" from
AC.
1.53ms
Return Home
0
1
X
Set DDRAM address to "00H"
from AC and return cursor to its
original position if shifted.
The contents of DDRAM are not
changed.
1.53ms
Entry Mode
Set
0
1
I/D
SH
Assign cursor moving direction
and make shift of entire display
enable.
39
s
Display
ON/OFF
Control
0
1
D
C
B
Set display(D), cursor(C), and
blinking of cursor(B) on/off
control bit.
39
s
Cursor or
Display Shift
0
1
S/C
R/L
X
Set cursor moving and display
shift control bit, and the direction,
without changing DDRAM data.
39
s
Function Set
0
1
DL
N
F
X
Set interface data length (DL : 4-
bit/8-bit), numbers of display line
(N : 1-line/2-line), display font
type(F : 5 X 8 dots/ 5 X 11 dots)
39
s
Set CGRAM
Address
0
1
AC5
AC4
AC3
AC2
AC1
AC0
Set CGRAM address in address
counter.
39
s
Set DDRAM
Address
0
1
AC6
AC5
AC4
AC3
AC2
AC1
AC0
Set DDRAM address in address
counter.
39
s
Read Busy
Flag and
Address
0
1
BF
AC6
AC5
AC4
AC3
AC2
AC1
AC0
Whether during internal operation
or not can be known by reading
BF. The contents of address
counter can also be read.
0
s
Write Data to
RAM
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Write data into internal RAM
(DDRAM/CGRAM).
43
s
Read Data
from RAM
1
D7
D6
D5
D4
D3
D2
D1
D0
Read data from internal RAM
(DDRAM/CGRAM).
43
s
NOTE: When an MPU program with checking the Busy Flag (DB7) is made, it must be necessary 1/2 fosc is necessary for
executing the next instruction by the falling edge of the 'E' signal after the Busy Flag (DB7) goes to "LOW".
相关PDF资料
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