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参数资料
| 型号： | S80486-DX4-75-S-V-8-B |
| 厂商： | ADVANCED MICRO DEVICES INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 75 MHz, MICROPROCESSOR, PQFP208 |
| 封装： | SQFP-208 |
| 文件页数： | 1/69页 |
| 文件大小： | 1070K |
| 代理商： | S80486-DX4-75-S-V-8-B |
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This document contains information on a product under development at Advanced Micro Devices. The information is
intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Advanced
Micro
Devices
DISTINCTIVE CHARACTERISTICS
n High-Performance Design
— Improved cache structure supports industry-
standard write-back cache
— Frequent instructions execute in one clock
— 80-million bytes/second burst bus at 25 MHz
— 105.6-million bytes/second burst bus at 33 MHz
— 128-million bytes/second burst bus at 40 MHz
— Flexible write-through and write-back address
control
— 0.5-micron CMOS process technology
— Dynamic bus sizing for 8-, 16-, and 32-bit buses
— Supports “soft reset” capability
n High On-Chip Integration
— 8-Kbyte unified code and data cache
— Floating-point unit
— Paged, virtual memory management
n Enhanced System and Power Management
— Stop clock control for reduced power
consumption
— Industry-standard 2-pin System Management In-
terrupt (SMI) for power management independent
of processor operating mode and operating
system
— Static design with Auto Halt power-down support
— Wide range of chipsets supporting SMM avail-
able to allow product differentiation
n Complete 32-Bit Architecture
— Address and data buses
— All registers
— 8-, 16-, and 32-bit data types
n Standard Features
— 3-V core with 5-V tolerant I/O
— Available in DX2 and DX4 versions
— Binary compatible with all Am486 DX
and Am486DX2 microprocessors
— Wide range of chipsets and support available
through the AMD FusionPCSM Program
n 168-pin PGA package or 208-pin SQFP package
n IEEE 1149.1 JTAG Boundary-Scan Compatibility
n Supports Environmental Protection Agency's
“Energy Star” program
— 3-V operation reduces power consumption up to
40%
— Energy management capability provides excel-
lent base for energy-efficient design
— Works with a variety of energy efficient, power
managed devices
GENERAL DESCRIPTION
The Enhanced Am486 microprocessor family is an ad-
dition to the Am486 microprocessor family of products.
The new family enhances system performance by incor-
porating a write-back cache implementation, flexible
clock control, and enhanced SMM. Table 1 shows avail-
able processors in the Enhanced Am486 microproces-
sor family.
The Enhanced Am486 microprocessor family cache al-
lows write-back configuration through software and
cacheable access control. On-chip cache lines are con-
figurable as either write-through or write-back.
The Enhanced CPU clock control feature permits the
CPU clock to be stopped under controlled conditions,
allowing reduced power consumption during system in-
activity. The SMM function is implemented with an indus-
try standard two-pin interface.
Table 1. Clocking Options
CPU
Type
Operating
Frequency
Bus Speed Available Package
DX2
66 MHz
33 MHz
168-pin PGA
80 MHz
40 MHz
DX4
75 MHz
25 MHz
168-pin PGA or
208-pin SQFP
100 MHz
33 MHz
120 MHz
40 MHz
168-pin PGA
PRELIMINARY
Enhanced Am486
Microprocessor Family
Publication#19225 Rev: C Amendment/0
Issue Date: March 1996
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