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| 型号： | S80486-DX4-75-S-V-8-B |
| 厂商： | ADVANCED MICRO DEVICES INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 75 MHz, MICROPROCESSOR, PQFP208 |
| 封装： | SQFP-208 |
| 文件页数： | 7/69页 |
| 文件大小： | 1070K |
| 代理商： | S80486-DX4-75-S-V-8-B |
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Enhanced Am486 Microprocessor
AMD
15
PRELIMINARY
FERR
Floating-Point Error (Active Low; Output)
Driven active when a floating-point error occurs, FERR
is similar to the ERROR pin on a 387 math coprocessor.
FERR is included for compatibility with systems using
DOS-type floating-point error reporting. FERR is active
Low, and is not floated during bus hold, except during
three-state test mode (see FLUSH).
FLUSH
Cache Flush (Active Low; Input)
In write-back mode, FLUSH forces the microprocessor
to write-back all modified cache lines and invalidate its
internal cache. The microprocessor generates two flush
acknowledge special bus cycles to indicate completion
of the write-back and invalidation. In write-through
mode, FLUSH invalidates the cache without issuing a
special bus cycle. FLUSH is an active Low input that
needs to be asserted only for one clock. FLUSH is asyn-
chronous, but setup and hold times t
20 and t21 must be
met for recognition in any specific clock. Sampling
FLUSH Low in the clock before the falling edge of RE-
SET causes the microprocessor to enter three-state test
mode.
HITM – New
Hit Modified Line (Active Low; Output)
In write-back mode (WB/WT=1 at RESET), HITM indi-
cates that an external snoop cache tag comparison hit
a modified line. When a snoop hits a modified line in the
internal cache, the microprocessor asserts HITM two
clocks after EADS is asserted. The HITM signal stays
asserted (Low) until the last BRDY for the correspond-
ing write-back cycle. At all other times, HITM is deas-
serted (High). During RESET, the HITM signal can be
used to detect whether the CPU is operating in write-
back mode. In write-back mode (WB/WT=1 at RESET),
HITM is deasserted (driven High) until the first snoop
that hits a modified line. In write-through mode, HITM
floats at all times.
HLDA
Hold Acknowledge (Active High; Output)
The HLDA signal is activated in response to a hold re-
quest presented on the HOLD pin. HLDA indicates that
the microprocessor has given the bus to another local
bus master. HLDA is driven active in the same clock in
which the microprocessor floats its bus. HLDA is driven
inactive when leaving bus hold. HLDA is active High and
remains driven during bus hold. HLDA is floated only
during three-state test mode. (See FLUSH.)
HOLD
Bus Hold Request (Active High; Input)
HOLD gives control of the microprocessor bus to anoth-
er bus master. In response to HOLD going active, the
microprocessor floats most of its output and input/output
pins. HLDA is asserted after completing the current bus
cycle, burst cycle, or sequence of locked cycles. The
microprocessor remains in this state until HOLD is deas-
serted. HOLD is active High and does not have an in-
ternal pull-down resistor. HOLD must satisfy setup and
hold times t18 and t19 for proper operation.
IGNNE
Ignore Numeric Error (Active Low; Input)
When this pin is asserted, the Enhanced Am486 micro-
processor will ignore a numeric error and continue ex-
ecuting non-control floating-point instructions. When
IGNNE is deasserted, the Enhanced Am486 micropro-
cessor will freeze on a non-control floating-point instruc-
tion if a previous floating-point instruction caused an
error. IGNNE has no effect when the NE bit in Control
Register 0 is set. IGNNE is active Low and is provided
with a small internal pullup resistor. IGNNE is asynchro-
nous but must meet setup and hold times t20 and t21 to
ensure recognition in any specific clock.
INTR
Maskable Interrupt (Active High; Input)
When asserted, this signal indicates that an external
interrupt has been generated. If the internal interrupt
flag is set in EFLAGS, active interrupt processing is ini-
tiated. The microprocessor generates two locked inter-
rupt acknowledge bus cycles in response to the INTR
pin going active. INTR must remain active until the in-
terrupt acknowledges have been performed to ensure
that the interrupt is recognized. INTR is active High and
is not provided with an internal pull-down resistor. INTR
is asynchronous, but must meet setup and hold times
t20 and t21 for recognition in any specific clock.
INV – New
Invalidate (Active High; Input)
The external system asserts INV to invalidate the
cache-line state when an external bus master proposes
a write. It is sampled together with A31–A4 during the
clock in which EADS is active. INV has an internal weak
pull-up. INV is ignored in write-through mode.
KEN
Cache Enable (Active Low; Input)
KEN determines whether the current cycle is cacheable.
When the microprocessor generates a cacheable cycle
and KEN is active one clock before RDY or BRDY during
the first transfer of the cycle, the cycle becomes a cache
line fill cycle. Returning KEN active one clock before
RDY during the last read in the cache line fill causes the
line to be placed in the on-chip cache. KEN is active
Low and is provided with a small internal pull-up resistor.
KEN must satisfy setup and hold times t
14 and t15 for
proper operation.
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