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参数资料
| 型号： | S80486-DX4-75-S-V-8-B |
| 厂商： | ADVANCED MICRO DEVICES INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 75 MHz, MICROPROCESSOR, PQFP208 |
| 封装： | SQFP-208 |
| 文件页数： | 18/69页 |
| 文件大小： | 1070K |
| 代理商： | S80486-DX4-75-S-V-8-B |
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AMD
25
PRELIMINARY
Enhanced Am486 Microprocessor
4.8.3
External Bus Master Snooping Actions
The following scenarios describe the snooping actions
of an external bus master.
4.8.3.1
Snoop Miss
Scenario: A snoop of the on-chip cache does not hit a
line, as shown in Figure 6.
Step 1 The microprocessor is placed in snooping
mode with HOLD. HLDA must be High for a
minimum of one clock cycle before EADS as-
sertion. In the fastest case, this means that
HOLD was asserted one clock cycle before the
HLDA response.
Step 2 EADS and INV are applied to the microprocessor. If
INV is 0, a read access caused the snooping cycle.
If INV is 1, a write access caused the snooping cycle.
Step 3 Two clock cycles after EADS was asserted, the
snooping signal HITM becomes valid. Because the
addressed line is not in the snooping cache, HITM is
1.
4.8.3.2
Snoop Hit to a Non-Modified Line
Scenario: The snoop of the on-chip cache hits a line, and the
line is not modified (see Figure 7).
Step 1 The microprocessor is placed in snooping
mode with HOLD. HLDA must be High for a
minimum of one clock cycle before EADS as-
sertion. In the fastest case, this means that
HOLD was asserted one clock cycle before the
HLDA response.
Step 2 EADS and INV are applied to the microprocessor. If
INV is 0, a read access caused the snooping cycle.
If INV is 1, a write access caused the snooping cycle.
Step 3 Two clock cycles after EADS is asserted, HITM
becomes valid. In this case, HITM is 1.
4.8.4
Write-Back Case
Scenario: Write-back accesses are always burst writes with
a length of four 32-bit words. For burst writes, the burst always
starts with the microprocessor line offset at 0. HOLD must be
deasserted before the write-back can be performed (see Fig-
ure 8).
Step 1 HOLD places the microprocessor in snooping
mode. HLDA must be High for a minimum of one
clock cycle before EADS assertion. In the fastest
case, this means that HOLD asserts one clock cy-
cle before the HLDA response.
Step 2 EADS and INV are asserted. If INV is 0, snooping
is caused by a read access. If INV is 1, snooping is
caused by a write access. EADS is not sampled
again until after the modified line is written back to
memory. It is detected again as early as in Step 11.
EADS
External
bus master’s
BOFF signal
HLDA
Data
HOLD
HITM
ADS
INV
BRDY
BLAST
W/R
M/IO
ADR
CLK
valid
n
n+4
n+8
n+12
n+1
valid
n
Figure 8. Snoop That Hits a Modified Line (Write-Back)
Note: The circled numbers in this figure represent the steps in section 4.8.4.
2
3
1
7
8
9
10
6
5
11
floating/three-stated
CACHE
floating/three-stated
4
n+8
n+4
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