参数资料
型号: S6A0078
元件分类: 显示控制器
英文描述: 34 X 120 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC183
封装: DIE-183
文件页数: 17/68页
文件大小: 328K
代理商: S6A0078
S6A0078
34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
24
Table 6. Instruction Set 1 (Continued)
Instruction
RE
Instruction Code
Description
Execu-
tion
Time
RS
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(fosc =
270kHz)
Function
Set
0
1
DL
N
RE
(0)
DH
REV
Set interface data length
(DL = "1": 8-bit, DL = "0": 4-bit),
numbers of display line when
NW = "0", (N = "1": 2-line, N = "0":
1-line), extension register, RE
("0"), shift/scroll enable
DH = "1": display shift enable
DH = "0": dot scroll enable.
reverse bit
REV = "1": reverse display,
REV = "0": normal display.
39
s
1
0
1
DL
N
RE
(1)
BE
0
Set DL, N, RE ("1") and
CGRAM/SEGRAM blink enable
(BE)
BE = " 1/0": CGRAM/SEGRAM
blink enable/disable
39
s
Set
CGRAM
address
0
1
AC5 AC4 AC3 AC2 AC1 AC0
Set CGRAM address in address
counter.
39
s
Set
SEGRAM
address
1
0
1
X
AC3 AC2 AC1 AC0
Set SEGRAM address in address
counter.
39
s
Set
DDRAM
address
0
1
AC6 AC5 AC4 AC3 AC2 AC1 AC0
Set DDRAM address in address
counter.
39
s
Set scroll
quantity
1
0
1
X
SQ5
SQ4
SQ3
SQ2
SQ1
SQ0
Set the quantity of horizontal dot
scroll.
39
s
Read busy
flag and
address
X
0
1
BF
AC6 AC5 AC4 AC3 AC2 AC1 AC0
Can be known whether during
internal operation or not by
reading BF. The contents of
address counter can also be read.
BF = "1": busy state,
BF = "0": ready state.
0
s
Write data
X
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Write data into internal RAM
(DDRAM/CGRAM/SEGRAM).
43
s
Read data
X
1
D7
D6
D5
D4
D3
D2
D1
D0
Read data from internal RAM
(DDRAM/CGRAM/SEGRAM).
43
s
NOTES:
1.
When an MPU program with busy flag (DB7) checking is m ode, 1/2 fosc (is necessary) for executing the next instruction
by the "E" signal after the busy flag (DB7) goes to "Low"
2.
"X" don't care
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