March 17, 2006S71PL-J_00_B3
S71PL-J Based MCPs
19
A d v a n c e I n f o r m a t i o n
MCP Revision Summary
Revision A (May 3, 2004)
Initial release.
Revision A1 (May 6, 2004)
MCP Features
Corrected the high performance access times.
Connection Diagrams
Added reference points on all diagrams.
Ordering I nformation
Corrected package types.
Corrected the description of product family to Page Mode Flash memory.
pSRAM Type 1
Corrected the description of the 8Mb device to 512Kb Word x 16-bit.
pSRAM Type 6
Corrected the description of the 2Mb device to 128Kb Word x 16-bit.
Corrected the description of the 4Mb device to 256Kb Word x 16-bit.
Revision A2 (May 11, 2004)
General Description
Corrected the tables to reflect accurate device configurations.
Revision A3 (June 16, 2004)
Ordering I nformation
Corrected the Valid Combinations tables to reflect accurate device configurations.
SRAM
New section added.
Revision A4 (July 16, 2004)
Global Changes
Global Change of FASL to Spansion.
Global change to remove space between M and Mb callouts.
“32Mb Flash Memory” on page 3
Replaced “S71PL032J08-07” with “S71PL032J08-0B”.
Replaced “S71PL032JA0” with “S71PL032JA0-07”.
Added row with the following content: S71PL032JA0-08; 65; 16Mb pSRAM; 70;
pSRAM3; TLC056.
“64Mb Flash Memory” on page 3
Replaced “
S71PL064J08-0K” with “S71PL064J08-0B”.
Replaced “
S71PL064J08-0P” with “S71PL064J08-0U”.
Deleted “S71PL064J80-05” row.
Replaced “
S71PL064JA0-07” with “S71PL064JA0-0K”.