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参数资料
| 型号： | S71WS256PD0HFFLW2 |
| 厂商： | Spansion Inc. |
| 英文描述： | based MCP/POP Products |
| 中文描述： | 基于MCP的/持久性有机污染物产品 |
| 文件页数： | 9/15页 |
| 文件大小： | 357K |
| 代理商： | S71WS256PD0HFFLW2 |
S75WS-P_00_02 September 6, 2006
S75WS-P based MCP/POP Products
7
D a t a
S h e e t
( A d v a n c e
I n f o r m a t i o n )
5.
Input/Output Descriptions
Table 5.1
identifies the input and output package connections provided on the device.
Table 5.1
Input/Output Descriptions (Sheet 1 of 2)
Symbol
Signal
Type
Description
WS
(NOR)
pSRAM
MS
(ORNAND)
Amax-A0
Input
NOR Flash Address inputs
X
X
DQ15-DQ0
I/O
Flash Data input/output, shared between NOR and ORNAND
Flash; shared with IO15-IO0 for ORNAND
X
X
X
F-CE#
Input
NOR Flash Chip-enable input #1. Asynchronous relative to CLK
for Burst Mode.
X
OE#
Output
Output Enable input. Asynchronous relative to CLK for Burst
mode.
X
X
WE#
Input
Write Enable input.
X
X
F-V
CC
Power
NOR Flash device power supply (1.7 V - 1.95V).
X
F-V
CCQ
Power
Input/Output Buffer power supply.
X
V
SS
RFU
Ground
Ground
X
X
X
—
Reserved for Future Use
RDY
Output
Flash ready output. Indicates the status of the Burst read. V
=
data valid. The Flash RDY pin is shared with the WAIT pin of the
pSRAM.
X
X
CLK
Input
NOR Flash Clock, shared with CLK of burst-mode pSRAM. The
first rising edge of CLK in conjunction with AVD# low latches the
address input and activates burst mode operation. After the initial
word is output, subsequent rising edges of CLK increment the
internal address counter. CLK should remain low during
asynchronous access.
X
X
AVD#
Input
NOR Flash Address Valid input. Shared with AVD# of burst-mode
pSRAM. Indicates to device that the valid address is present on
the address inputs.
V
= for asynchronous mode, indicates valid address; for burst
mode, causes starting address to be latched on rising edge of
CLK.
V
IH
= device ignores address inputs
X
X
F-RST#
Input
NOR Flash hardware reset input. V
IL
= device resets and returns
to reading array data
X
F-WP#
Input
NOR Flash hardware write protect input. V
= disables program
and erase functions in the four outermost sectors.
X
F-ACC
Input
NOR Flash accelerated input. At V
, accelerates programming;
automatically places device in unlock bypass mode. At V
IL
,
disables all program and erase functions. Should be at V
IH
for all
other conditions.
X
R-CE#
Input
Chip-enable input for pSRAM
X
R-MRS
Input
Mode Select Register (pSRAM). For Type 2 only.
X
R-V
CC
Power
pSRAM Power Supply
X
R-UB#
Input
Upper Byte Control (pSRAM)
X
R-LB#
Input
Lower Byte Control (pSRAM)
X
DNU
—
Do Not Use
N-CLE
Input
Command Latch Enable: The CLE input signal is used to control
loading of the operation mode command into the internal
command register. The command is latched into the command
register from the I/O port on the rising edge of the WE# signal
while CE# is low and CLE is High.
X
N-ALE
Input
Address Latch Enable: The ALE signal is used to control loading
of either address information or input data into the internal
address/data register. Address information is latched on the rising
edge of WE# if CE# is low and ALE is High.
Input data is latched if CE# is low and ALE is Low.
X
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