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参数资料
型号： S80C196EA
厂商： INTEL CORP
元件分类： 微控制器/微处理器
英文描述： 16-BIT, MICROCONTROLLER, PQFP16
封装： QFP-160
文件页数： 9/32页
文件大小： 869K
代理商： S80C196EA
Preliminary Datasheet
13
80C196EA -
Commercial
6.2
AC Characteristics — Multiplexed Bus Mode
Test Conditions: Capacitive load on all pins = 50 pF, Rise and Fall Times = 3 ns.
Table 7. AC Characteristics, Multiplexed Bus Mode (Sheet 1 of 2)
Symbol
Parameter
Min
Max
Units
FXTAL1
Frequency on XTAL1, PLL in 1x mode
20
40
MHz (1, 8)
Frequency on XTAL1, PLL in 2x mode
10
20
MHz (8)
f
Operating frequency, f = FXTAL1; PLL in 1x mode
20
40
MHz (8)
Operating frequency, f = 2FXTAL1; PLL in 2x mode
t
Period, t = 1/f
25
50
ns
TAVDV
Address Valid to Input Data Valid
3t – 40
ns (2)
TRLDV
RD# Low to Input Data Valid
t – 18
ns (2)
TCHDV
CLKOUT High to Input Data valid
2t – 35
ns (9)
TRHDZ
RD# High to Input Data Float
t + 5
ns
TRXDX
Data Hold after RD# Inactive
0
ns
TXHCH
XTAL1 Rising Edge to CLKOUT High or Low
3
50
ns (9)
TCLCL
CLKOUT Cycle Time
2t
ns (9)
TCHCL
CLKOUT High Period
t – 10
t + 10
ns (9)
TCLLH
CLKOUT Falling to ALE Rising
– 10
10
ns (9)
TLLCH
ALE Falling to CLKOUT Rising
– 10
10
ns (9)
TLHLH
ALE Cycle Time
4t
ns (2)
TLHLL
ALE High Period
t – 10
t + 10
ns
TAVLL
Address Setup to ALE Low
t – 15
ns
TLLAX
Address Hold after ALE Low
t – 15
ns
TLLRL
ALE Low to RD# Low
t – 15
ns
TRLCL
RD# Low to CLKOUT Low
– 10
10
ns (9)
TRLRH
RD# Low to RD# High
t – 12
ns (2)
TRHLH
RD# High to ALE Rising
t – 5
t + 15
ns (3)
TRLAZ
RD# Low to Address Float
5
ns
TLLWL
ALE Low to WR# Low
t – 12
ns
TQVWH
Data Stable to WR# Rising Edge
t – 14
ns (2)
TCHWH
CLKOUT High to WR# Rising Edge
– 10
10
ns (9)
TWLWH
WR# Low to WR# High
t – 10
ns (2)
NOTES:
1. 20 MHz is the maximum input frequency when using an external crystal oscillator; however, 40 MHz can be
applied with an external clock source.
2. If wait states are used, add 2t
× n, where n = number of wait states.
3. Assuming back-to-back bus cycles.
4. When forcing wait states using the BUSCON register, add 2t
× n.
5. Exceeding the maximum specification causes additional wait states.
6. 8-bit bus only.
7. The first falling edge of READY is not synchronized to a CLKOUT edge; therefore, one programmed wait
state is required.
8. Device is static by design but has been tested only down to 20 MHz.
9. Assumes CLKOUT is operating in divide-by-two mode (f/2).
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