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参数资料
| 型号： | SAF-C868A-1SGBA |
| 厂商： | INFINEON TECHNOLOGIES AG |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, 40 MHz, MICROCONTROLLER, PDSO28 |
| 封装： | PLASTIC, SO-28 |
| 文件页数： | 9/82页 |
| 文件大小： | 1252K |
| 代理商： | SAF-C868A-1SGBA |
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C868
Data Sheet
17
V 1.0, 2003-05
Bootstrap loader
The C868, includes a bootstrap mode, which is activated by setting the ALE/BSL pin at
logic low with a pulldown and TxD pin at logic high with a pullup at the rising edge of the
RESET. Or it can be entered by software, that is by setting BSLEN bit and resetting
SWAP bit in SFR SYSCON1 accompany by an unlock sequence.
In the bootstrap mode, software routines of the bootstrap loader located in the boot ROM
will be executed. Its purpose is to allow the easy and quick programming of the internal
SRAM (0000H to 1FFFH) or XRAM (FF00H to FFFFH) via serial interface (UART) while
the MCU is in-circuit. It also provides a way to program SRAM or XRAM through
bootstrapping from an external SPI or I2C EEPROM.
The first action of the bootstrap loader is to detect the presence of EEPROM and its type,
SPI or I2C, and check the first byte of the serial EEPROM. If the first byte is 0A5H, the
MCU would enter Phase A to download from the EEPROM. Otherwise, it will enter
Phase B to establish a serial communication with the connected host. Bootstrapping
from the serial EEPROM can also be done in phase B if it is invoked by the host.
Phase B consists of two functional parts that represent two phases:
Phase I: Establish a serial connection and automatically synchronize to the transfer
speed (baud rate) of the serial communication partner (host).
Phase II: Perform the serial communication with the host. The host controls the
communication by sending special header information, which select one of the
working modes. These modes are:
The phases of the bootstrap loader are illustrated in Figure 7.
Table 4
Serial Communication Modes of Phase B
Modes
Description
0
Transfer a customer program from the host to the SRAM (0000H to
1FFFH) or XRAM (FF00H -FFFFH). Then return to the beginning of
phase II and wait for the next command from the host.
1
Execute a customer program in the XRAM at start address FF00H.
2
Execute a customer program in the SRAM at start address 0000H.
3
Transfer a customer program from the SPI EEPROM to the SRAM
(0000H to 1FFFH) or XRAM (FF00H -FFFFH). Then return to the
beginning of phase II and wait for the next command from the host.
4
Transfer a customer program from the I2C EEPROM to the SRAM
(0000H to 1FFFH) or XRAM (FF00H -FFFFH). Then return to the
beginning of phase II and wait for the next command from the host.
5-9
reserved
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