参数资料
型号: SAF-XC164SM-16F40F
厂商: INFINEON TECHNOLOGIES AG
元件分类: 微控制器/微处理器
英文描述: 16-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP64
封装: 0.50 MM PITCH, GREEN, PLASTIC, TQFP-64
文件页数: 57/67页
文件大小: 1960K
代理商: SAF-XC164SM-16F40F
XC164SM
Derivatives
Electrical Parameters
Data Sheet
58
V1.2, 2007-03
This is especially important for bus cycles using waitstates and e.g. for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter
is negligible.
The value of the accumulated PLL jitter depends on the number of consecutive VCO
output cycles within the respective timeframe. The VCO output clock is divided by the
output prescaler (K = PLLODIV+1) to generate the master clock signal
f
MC. Therefore,
the number of VCO cycles can be represented as K
× N, where N is the number of
consecutive
f
MC cycles (TCM).
For a period of N
× TCM the accumulated PLL jitter is defined by the deviation D
N:
DN [ns] = ±(1.5 + 6.32 × N / fMC); fMC in [MHz], N = number of consecutive TCMs.
So, for a period of 3 TCMs @ 20 MHz and K = 12: D3 = ±(1.5 + 6.32 × 3 / 20) = 2.448 ns.
This formula is applicable for K
× N < 95. For longer periods the K × N = 95 value can be
used. This steady value can be approximated by: DNmax [ns] = ±(1.5 + 600 / (K × fMC)).
Figure 15
Approximated Accumulated PLL Jitter
Note: The bold lines indicate the minimum accumulated jitter which can be achieved by
selecting the maximum possible output prescaler factor K.
MCD05566
N
0
±1
±2
±3
±4
±5
±6
±7
±8
Acc. jitter
D
N
05
10
15
20
25
ns
K = 15
K = 12
K = 10
K = 8
K = 6 K = 5
1
10 MHz
20 MHz
40 MHz
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相关代理商/技术参数
参数描述
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SAF-XC164SM-4F40F 制造商:Infineon Technologies AG 功能描述:16BIT MCU 32K FLASH SMD 164SM-4