参数资料
型号: SAK-TC1767-256F133HL
厂商: INFINEON TECHNOLOGIES AG
元件分类: 微控制器/微处理器
英文描述: 32-BIT, FLASH, 133 MHz, RISC MICROCONTROLLER, PQFP176
封装: 0.50 MM PITCH, GREEN, PLASTIC, LQFP-176
文件页数: 122/126页
文件大小: 826K
代理商: SAK-TC1767-256F133HL
TC1767
Electrical Parameters
Data Sheet
91
V1.3, 2009-09
Figure 17
ADC0/ADC1 Clock Circuit
12) Only one of these parameters is tested, the other is verified by design characterization.
13) The leakage current decreases typically 30% for junction temperature decrease of 10
oC.
14) Applies to AINx, when used as auxiliary reference inputs.
15)
I
AREF_MAX is valid for the minimum specified conversion time. The current flowing during an ADC conversion
with a duration of up to
t
C = 25s can be calculated with the formula IAREF_MAX = QCONV/tC. Every conversion
needs a total charge of
Q
CONV = 150pC from VAREF.
All ADC conversions with a duration longer than
t
C = 25s consume an IAREF_MAX = 6A.
16) For the definition of the parameters see also Figure 18.
17) This represents an equivalent switched capacitance. This capacitance is not switched to the reference voltage
at once. Instead of this smaller capacitances are successively switched to the reference voltage.
18) The sampling capacity of the conversion C-Network is pre-charged to
V
AREF/2 before the sampling moment.
Because of the parasitic elements the voltage measured at AINx can deviate from
V
AREF/2, and is typically
1.35V.
19)
R
AIN7T = 1400 Ohm maximum and 830 Ohm typical in the VDDM =3.3V± 5% range.
20) The DC current at the pin is limited to 3 mA for the operational lifetime.
ADC_clocking
analog part
analog clock
fADCI
digital clock
fADCD
fADC
arbiter
divider for
fADCD
registers
interrupts,
etc.
clock
generation
divider for
fADCI
ADC kernel
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SAK-TC1767-256F133HLAD 制造商:Infineon Technologies AG 功能描述:
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