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| 型号： | SC120SKTRT |
| 厂商： | Semtech |
| 文件页数： | 24/32页 |
| 文件大小： | 0K |
| 描述： | IC REG BST SYNC 3.3V/ADJ SOT23-6 |
| 标准包装： | 1 |
| 类型： | 升压（升压） |
| 输出类型： | 两者兼有 |
| 输出数： | 1 |
| 输出电压： | 3.3V，1.8 V ~ 5 V |
| 输入电压： | 0.7 V ~ 4.5 V |
| 频率 - 开关： | 1.2MHz |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | SOT-23-6 |
| 包装： | 标准包装 |
| 供应商设备封装： | SOT-23-6 |
| 产品目录页面： | 1357 (CN2011-ZH PDF) |
| 其它名称： | SC120SKDKR |
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SC120
Applications Information (continued)
pause at a reduced output voltage until the load is reduced
further.
Output Overload and Recovery
When in PSAVE operation, an increasing load will eventu-
ally satisfy one of the PSAVE exit criteria and regulation
will revert to PWM operation. As previously noted, the
PWM steady state duty cycle is determined by
D = 1 – (V IN /V OUT ), but must be somewhat greater in prac-
tice to overcome dissipative losses. As the output load
increases, the dissipative losses also increase. The PWM
controller must increase the duty cycle to compensate.
Eventually, one of two overload conditions will occur,
determined by V IN , V OUT , and the overall dissipative losses
due to the output load current. Either the maximum duty
cycle of 90% will be reached or the n-channel FET 1.2A
(nominal) peak current limit will be reached, which effec-
tively limits the duty cycle to a lower value. Above that
load, the output voltage will decrease rapidly and in
reverse order the startup current limits will be invoked as
the output voltage falls through its various voltage thresh-
olds. How far the output voltage drops depends on the
load voltage vs. current characteristic.
A reduction in input voltage, such as a discharging battery,
will lower the load current at which overload occurs.
Lower input voltage increases the duty cycle required to
produce a given output voltage. And lower input voltage
also increases the input current to maintain the input
power, which increases dissipative losses and further
increases the required duty cycle. Therefore an increase in
load current or a decrease in input voltage can result in
output overload. Once an overload has occurred, the load
must be decreased to permit recovery. The conditions
required for overload recovery are identical to those
required for successful initial startup.
viding a moderate resistance path across the inductor to
dampen the oscillations at the LX pin. This effectively
reduces EMI that can develop from the resonant circuit
formed by the inductor and the drain capacitance at LX.
The anti-ringing circuitry is disabled between PSAVE
bursts.
Component Selection
The SC120 provides optimum performance when a 4.7μH
inductor is used with a 10μF output capacitor. Different
component values can be used to modify PSAVE exit or
entry loads, modify output voltage ripple in PWM mode,
improve transient response, or to reduce component size
or cost.
Inductor Selection
The inductance value primarily affects the amplitude of
inductor current ripple ( Δ I L ). Reducing inductance
increases Δ I L . This raises the inductor peak current,
I L-max = I L-avg + Δ I L /2, where I L-avg is the inductor current aver-
aged over a full on/off cycle. I L-max is subject to the
n-channel FET current limit I LIM(N) , therefore reducing the
inductance may lower the output overload current thresh-
old. Increasing Δ I L also lowers the inductor minimum
current, I L-min = I L-avg – Δ I L /2, thus raising the PSAVE entry
load current threshold. This is the output load below
which I L-min = 0, the boundary between continuous mode
and discontinuous mode PWM regulation, which signals
the SC120 controller to switch to PSAVE operation. In the
extreme case of V IN approaching V OUT , smaller inductance
can also reduce the PSAVE inductor burst-envelope current
ripple and voltage ripple.
Equate input power to output power, note that input
current equals inductor current, and average over a full
PWM switching cycle to obtain
Anti-ringing Circuitry
In PWM operation, the n-channel and p-channel FETs are
simultaneously turned off when the inductor current
I L
avg
1 V OUT I OUT
V IN
reaches zero. They remain off for the zero-inductor-
current portion of the off-state. Note that discontinuous
mode is a marginal-load condition, which if persistent will
trigger a transition to PSAVE operation.
When both FET switches are simultaneously turned off, an
where η is effi ciency.
Δ I L is the inductor (and thus the input) peak-to-peak
current. Neglecting the n-channel FET R DS-ON and the
inductor DCR, for duty cycle D, and with T = 1/f osc ,
internal switch between the IN and LX pins is closed, pro-
24
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