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| 型号： | SC120SKTRT |
| 厂商： | Semtech |
| 文件页数： | 26/32页 |
| 文件大小： | 0K |
| 描述： | IC REG BST SYNC 3.3V/ADJ SOT23-6 |
| 标准包装： | 1 |
| 类型： | 升压（升压） |
| 输出类型： | 两者兼有 |
| 输出数： | 1 |
| 输出电压： | 3.3V，1.8 V ~ 5 V |
| 输入电压： | 0.7 V ~ 4.5 V |
| 频率 - 开关： | 1.2MHz |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | SOT-23-6 |
| 包装： | 标准包装 |
| 供应商设备封装： | SOT-23-6 |
| 产品目录页面： | 1357 (CN2011-ZH PDF) |
| 其它名称： | SC120SKDKR |
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SC120
Applications Information (continued)
formance), will ensure correct mode–switching behavior.
For very low V IN (0.7V to 0.8V) such as is obtained with a
nearly-depleted single-cell alkaline battery), a smaller
value of inductance will help to ensure that PWM mode
will switch to PSAVE mode as the load decreases. This
consideration may be of little importance in most applica-
tions, as there is little energy remaining in such a deeply
at the switching frequency of the SC120. Ceramic capaci-
tors of type Y5V are not recommended as their tempera-
ture coeffi cients and large capacitance tolerance make
them unsuitable for this application. The following table
lists recommended capacitors. For smaller values and
smaller packages, it may be necessary to use multiple
devices in parallel, especially for C OUT .
discharged battery.
The following table lists the manufacturers of recom-
mended inductor options. The specification values shown
are simplified approximations or averages of many device
parameters under various test conditions. See manufac-
turers’ documentation for full performance data.
Manufacturer/
Part Number
Murata
GRM21BR60J226ME39B
Murata
GRM31CR71A226KE15L
Murata
GRM185R60G475ME15
Value
(μF)
22
22
4.7
Rated Volt-
age (VDC)
6.3
10
4
Type
X5R
X7R
X5R
Case
Size
0805
1206
0603
Case
Height
(mm)
1.25
1.6
0.5
Manufacturer/
Part #
Value
(μH)
DCR
(Ω)
Rated
Current
(mA)
Tolerance
(%)
Dimensions
LxWxH
(mm)
TDK
C2012X5R1A226M
Taiyo Yuden
JMK212BJ226MG-T
22
22
10
20
X5R
X5R
0805
0805
0.85
1.25
Murata
LQM31PN4R7M00
Coilcraft
XFL2006-472
4.7
4.7
0.3
0.7
700
500
20
20
3.2 x 1.6 x 0.95
2 x 2 x 0.6
PCB Layout Considerations
Poor layout can degrade the performance of the DC-DC
converter and can contribute to EMI problems, ground
Capacitor Selection
Input and output capacitors must be chosen carefully to
ensure that they are of the correct value and rating. The
output capacitor requires a minimum capacitance value
of 10μF at the programmed output voltage to ensure sta-
bounce, and resistive voltage losses. Poor regulation and
instability can result.
The following simple design rules can be implemented to
ensure good layout:
bility over the full operating range, and to ensure positive
mode-switching hysteresis. The DC bias must be included
in capacitor derating to ensure the required effective
capacitance is provided, especially when considering
small package-size capacitors. For example, a 10μF 0805
capacitor may provide suffi cient capacitance at low output
voltages but may be too low at higher output voltages.
Therefore, a higher capacitance value may be required to
provide the minimum of 10μF at these higher output volt-
ages. Additional output capacitance may be required for
V IN close to V OUT to reduce ripple in PSAVE mode, to increase
the PSAVE exit threshold for high V IN , and to ensure stabil-
ity in PWM mode, especially at higher output load
currents.
?
?
?
?
Place the inductor and filter capacitors as close
to the device as possible and use short wide
traces between the power components.
Route the output voltage feedback path away
from the inductor and LX node to minimize
noise and magnetic interference.
Maximize ground metal on the component side
to improve the return connection and thermal
dissipation. Separation between the LX node
and GND should be maintained to avoid cou-
pling capacitance between the LX node and the
ground plane.
Use a ground plane with several vias connecting
to the component side ground to further reduce
Low ESR capacitors such as X5R or X7R type ceramic
capacitors are recommended for input bypassing and
output filtering. Low-ESR tantalum capacitors are not rec-
ommended due to possible reduction in capacitance seen
noise interference on sensitive circuit nodes.
A layout drawing for the MLP package is shown in Figure 4
and a layout drawing for the SOT23 package is shown in
Figure 5.
26
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