参数资料
型号: SC16C2550IN40,112
厂商: NXP Semiconductors
文件页数: 20/46页
文件大小: 0K
描述: IC UART DUAL W/FIFO 40-DIP
标准包装: 9
特点: 2 通道
通道数: 2,DUART
FIFO's: 16 字节
电源电压: 2.5V,3.3V,5V
带自动流量控制功能:
带IrDA 编码器/解码器:
带故障启动位检测功能:
带调制解调器控制功能:
带CMOS:
安装类型: 通孔
封装/外壳: 40-DIP(0.600",15.24mm)
供应商设备封装: 40-DIP
包装: 管件
其它名称: 568-3262-5
935270024112
SC16C2550IN40
Philips Semiconductors
SC16C2550
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
encoder/decoder
Product data
Rev. 03 — 19 June 2003
27 of 46
9397 750 11621
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
[1]
Whenever any MSR bit 0-3 is set to logic 1, a Modem Status Interrupt will be generated.
7.9 Scratchpad Register (SPR)
The SC16C2550 provides a temporary data register to store 8 bits of user
information.
7.10 Enhanced Feature Register (EFR)
Enhanced features are enabled or disabled using this register.
Bits 0 through 4 provide single or dual character software ow control selection.
When the Xon1 and Xon2 and/or Xoff1 and Xoff2 modes are selected, the double
8-bit words are concatenated into two sequential numbers.
1
MSR[1]
DSR [1]
Logic 0 = No DSR change (normal default condition).
Logic1=The DSR input to the SC16C2550 has changed state
since the last time it was read. A modem Status Interrupt will be
generated.
0
MSR[0]
CTS [1]
Logic 0 = No CTS change (normal default condition).
Logic 1 = The CTS input to the SC16C2550 has changed state
since the last time it was read. A modem Status Interrupt will be
generated.
Table 19:
Modem Status Register bits description…continued
Bit
Symbol
Description
Table 20:
Enhanced Feature Register bits description
Bit
Symbol
Description
7
EFR[7]
Automatic CTS ow control.
Logic0=Automatic CTS ow control is disabled (normal default
condition).
Logic 1 = Enable Automatic CTS ow control. Transmission will stop
when CTS goes to a logical 1. Transmission will resume when the CTS
pin returns to a logical 0.
6
EFR[6]
Automatic RTS ow control. Automatic RTS may be used for hardware ow
control by enabling EFR[6]. When Auto-RTS is selected, an interrupt will
be generated when the receive FIFO is lled to the programmed trigger
level and RTS will go to a logic 1 at the next trigger level. RTS will return to
a logic 0 when data is unloaded below the next lower trigger level
(programmed trigger level 1). The state of this register bit changes with the
status of the hardware ow control. RTS functions normally when
hardware ow control is disabled.
0 = Automatic RTS ow control is disabled (normal default condition).
1 = Enable Automatic RTS ow control.
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