参数资料
型号: SC16C550BIA44,518
厂商: NXP Semiconductors
文件页数: 45/48页
文件大小: 0K
描述: IC UART SINGLE W/FIFO 44-PLCC
产品培训模块: Stand-Alone UARTs
标准包装: 1
特点: 可编程
通道数: 1,UART
FIFO's: 16 字节
电源电压: 2.5V,3.3V,5V
带自动流量控制功能:
带故障启动位检测功能:
带调制解调器控制功能:
带CMOS:
安装类型: 表面贴装
封装/外壳: 44-LCC(J 形引线)
供应商设备封装: 44-PLCC
包装: 标准包装
产品目录页面: 827 (CN2011-ZH PDF)
其它名称: 568-2039-6
SC16C550B_5
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 1 October 2008
6 of 48
NXP Semiconductors
SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Type
Description
PLCC44 LQFP48 DIP40 HVQFN32
A0
31
28
19
I
Register select. A2 to A0 are used during read and write
operations to select the UART register to read from or
write to. Refer to Table 3 for register addresses and refer to
AS description.
A1
30
27
18
A2
29
26
17
AS
28
24
25
-
I
Address strobe. When AS is active (LOW), A0, A1, and
A2 and CS0, CS1, and CS2 drive the internal select logic
directly; when AS is HIGH, the register select and chip
select signals are held at the logic levels they were in when
the LOW-to-HIGH transition of AS occurred.
BAUDOUT
17
12
15
-
O
Baud out. BAUDOUT is a 16
× clock signal for the
transmitter section of the UART. The clock rate is
established by the reference oscillator frequency divided
by a divisor specied in the baud generator divisor latches.
BAUDOUT may also be used for the receiver section by
tying this output to RCLK. In HVQFN32 package
BAUDOUT and RCLK are bonded internally.
CS0[2]
14
9
12
-
I
Chip select. When CS0 and CS1 are HIGH and CS2 is
LOW, these three inputs select the UART. When any of
these inputs are inactive, the UART remains inactive (refer
to AS description).
CS1[2]
15
10
13
-
CS2[2]
16
11
14
-
CS[2]
---
8
40
38
36
24
I
Clear to send. CTS is a modem status signal. Its condition
can be checked by reading bit 4 (CTS) of the Modem
Status Register. Bit 0 (CTS) of the Modem Status Register
indicates that CTS has changed states since the last read
from the Modem Status Register. If the modem status
interrupt is enabled when CTS changes levels and the
auto-CTS mode is not enabled, an interrupt is generated.
This pin has no effect on the UART’s transmit or receive
operation.
D7 to D0
9, 8, 7,
6, 5, 4,
3, 2
4, 3, 2,
47, 46,
45, 44,
43
8, 7,
6, 5,
4, 3,
2, 1
5, 4, 3, 1,
32, 31,
30, 29
I/O
Data bus. Eight data lines with 3-state outputs provide a
bidirectional path for data, control and status information
between the UART and the CPU.
DCD[2]
42
40
38
26
I
Data carrier detect. DCD is a modem status signal. Its
condition can be checked by reading bit 7 (DCD) of the
Modem Status Register. Bit 3 (DCD) of the Modem Status
Register indicates that DCD has changed states since the
last read from the Modem Status Register. If the modem
status interrupt is enabled when DCD changes levels, an
interrupt is generated.
DDIS
26
22
23
-
O
Driver disable. DDIS is active (LOW) when the CPU is
reading data. When inactive (HIGH), DDIS can disable an
external transceiver.
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