参数资料
型号: SC16C554BIB80
厂商: NXP Semiconductors N.V.
元件分类: 收发器
英文描述: 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit-s (max.) with 16-byte FIFOs
封装: SC16C554BIB64<SOT314-2 (LQFP64)|<<http://www.nxp.com/packages/SOT314-2.html<1<week 36, 2004,;SC16C554BIB64<SOT314-2 (LQFP64)|<<http://www.nxp.com/packages/SOT314-2.html&l
文件页数: 14/58页
文件大小: 1035K
代理商: SC16C554BIB80
SC16C554B_554DB
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 4 — 8 June 2010
14 of 58
NXP Semiconductors
SC16C554B/554DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
[1]
HVQFN48 package die supply ground is connected to both GND pins and exposed center pad. GND pins must be connected to supply
ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be
soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias
need to be incorporated in the PCB in the thermal pad region.
TXA
TXB
TXC
TXD
17
19
51
53
8
10
39
41
29
32
69
72
6
8
32
34
O
O
O
O
Transmit data A, B, C, D.
These outputs are
associated with individual serial transmit channel data
from the SC16C554B/554DB. The TX signal will be a
logic 1 during reset, idle (no data), or when the
transmitter is disabled. During the local Loopback
mode, the TXn output pin is disabled and TX data is
internally connected to the UART RX input.
Transmit Ready (active LOW).
TXRDY contains the
wire-ORed status of all four transmit channel FIFOs,
TXRDYA to TXRDYD. A logic 0 indicates a buffer ready
status, that is, at least one location is empty and
available in one of the TX channels (A to D). This pin
goes to a logic 1 when all four channels have no more
empty locations in the TX FIFO or THR. Individual
channel TX status can be read by examining individual
internal registers via CS and A0 to A4 pin functions.
The TXRDY pin is not available on the HVQFN48
package.
Power supply inputs.
TXRDY
39
-
55
-
O
V
CC
13, 30,
47, 64
35
4, 21,
35, 52
25
5, 25,
45, 65
50
2, 28
I
XTAL1
18
I
Crystal or external clock input.
Functions as a crystal
input or as an external clock input. A crystal can be
connected between this pin and XTAL2 to form an
internal oscillator circuit (see
Figure 13
). Alternatively,
an external clock can be connected to this pin to
provide custom data rates. (See
Section 6.6
“Programmable baud rate generator”
.)
Output of the crystal oscillator or buffered clock.
(See also XTAL1.) Crystal oscillator output or buffered
clock output.
XTAL2
36
26
51
19
O
Table 2.
Symbol
Pin description
…continued
Pin
PLCC68
Type
Description
LQFP64
LQFP80 HVQFN48
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