参数资料
型号: SC16C554DBIB64
厂商: NXP Semiconductors N.V.
元件分类: 收发器
英文描述: 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit-s (max.) with 16-byte FIFOs
封装: SC16C554BIB64<SOT314-2 (LQFP64)|<<http://www.nxp.com/packages/SOT314-2.html<1<week 36, 2004,;SC16C554BIB64<SOT314-2 (LQFP64)|<<http://www.nxp.com/packages/SOT314-2.html&l
文件页数: 11/58页
文件大小: 1035K
代理商: SC16C554DBIB64
SC16C554B_554DB
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 4 — 8 June 2010
11 of 58
NXP Semiconductors
SC16C554B/554DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
CTSA
CTSB
CTSC
CTSD
11
25
45
59
2
16
33
47
23
38
63
78
1
12
26
-
I
I
I
I
Clear to Send (active LOW).
These inputs are
associated with individual UART channels A to D. A
logic 0 on the CTSn pin indicates the modem or data
set is ready to accept transmit data from the
SC16C554B/554DB. Status can be tested by reading
MSR[4]. This pin only affects the transmit or receive
operations when auto-CTS function is enabled via
MCR[5] for hardware flow control operation.
Data bus (bidirectional).
These pins are the 8-bit,
3-state data bus for transferring information to or from
the controlling CPU. D0 is the least significant bit and
the first data bit in a transmit or receive serial data
stream.
D0
D1
D2
D3
D4
D5
D6
D7
DSRA
DSRB
DSRC
DSRD
66
67
68
1
2
3
4
5
10
26
44
60
53
54
55
56
57
58
59
60
1
17
32
48
7
8
9
11
12
13
14
15
22
39
62
79
39
40
41
42
43
44
45
46
-
-
25
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
Data Set Ready (active LOW).
These inputs are
associated with individual UART channels, A through
D. A logic 0 on this pin indicates the modem or data set
is powered-on and is ready for data exchange with the
UART. This pin has no effect on the UART’s transmit or
receive operation.
Data Terminal Ready (active LOW).
These outputs
are associated with individual UART channels, A
through D. A logic 0 on this pin indicates that the
SC16C554B/554DB is powered-on and ready. This pin
can be controlled via the Modem Control Register.
Writing a logic 1 to MCR[0] will set the DTRn output to
logic 0, enabling the modem. This pin will be a logic 1
after writing a logic 0 to MCR[0], or after a reset. This
pin has no effect on the UART’s transmit or receive
operation.
Signal and power ground.
DTRA
DTRB
DTRC
DTRD
12
24
46
58
3
15
34
46
24
37
64
77
-
-
27
-
O
O
O
O
GND
6, 23,
40, 57
15
21
49
55
14, 28,
45, 61
6
12
37
43
16, 36,
56, 76
27
34
67
74
21, 37,
47
[1]
4
10
30
36
I
INTA
INTB
INTC
INTD
O
O
O
O
Interrupt A, B, C, D (active HIGH).
This function is
associated with the 16 mode only. These pins provide
individual channel interrupts INTA to INTD.
INTA to INTD are enabled when MCR[3] is set to a
logic 1, interrupts are enabled in the Interrupt Enable
Register (IER), and when an interrupt condition exists.
Interrupt conditions include: receiver errors, available
receiver buffer data, transmit buffer empty, or when a
modem status flag is detected. When the 68 mode is
selected, the functions of these pins are re-assigned.
68 mode functions are described under their respective
name/pin headings.
Table 2.
Symbol
Pin description
…continued
Pin
PLCC68
Type
Description
LQFP64
LQFP80 HVQFN48
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