参数资料
型号: SC16C554DBIB64
厂商: NXP Semiconductors N.V.
元件分类: 收发器
英文描述: 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit-s (max.) with 16-byte FIFOs
封装: SC16C554BIB64<SOT314-2 (LQFP64)|<<http://www.nxp.com/packages/SOT314-2.html<1<week 36, 2004,;SC16C554BIB64<SOT314-2 (LQFP64)|<<http://www.nxp.com/packages/SOT314-2.html&l
文件页数: 13/58页
文件大小: 1035K
代理商: SC16C554DBIB64
SC16C554B_554DB
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 4 — 8 June 2010
13 of 58
NXP Semiconductors
SC16C554B/554DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
RESET
(RESET)
37
27
53
20
I
Reset.
In the 16 mode, a logic 1 on this pin will reset
the internal registers and all the outputs. The UART
transmitter output and the receiver input will be
disabled during reset time. (See
Section 7.10
“SC16C554B/554DB external reset conditions”
for
initialization details.) When 16/68 is a logic 0
(68 mode), this pin functions similarly, bus as an
inverted reset interface signal, RESET.
Ring Indicator (active LOW).
These inputs are
associated with individual UART channels, A to D. A
logic 0 on this pin indicates the modem has received a
ringing signal from the telephone line. A logic 1
transition on this input pin will generate an interrupt.
RIA
RIB
RIC
RID
RTSA
RTSB
RTSC
RTSD
8
28
42
62
14
22
48
56
63
19
30
50
5
13
36
44
18
43
58
3
26
35
66
75
-
-
23
-
3
11
29
-
I
I
I
I
O
O
O
O
Request to Send (active LOW).
These outputs are
associated with individual UART channels, A to D. A
logic 0 on the RTSn pin indicates the transmitter has
data ready and waiting to send. Writing a logic 1 in the
Modem Control Register MCR[1] will set this pin to a
logic 0, indicating data is available. After a reset this pin
will be set to a logic 1. This pin only affects the transmit
and receive operations when auto-RTS function is
enabled via MCR[5] for hardware flow control
operation.
Read/Write strobe.
This function is associated with the
68 mode only. This pin provides the combined functions
for Read or Write strobes.
Logic 1 = Read from UART register selected by CS and
A0 to A4.
Logic 0 = Write to UART register selected by CS and
A0 to A4.
Receive data input RXA to RXD.
These inputs are
associated with individual serial channel data to the
SC16C554B/554DB. The RXn signal will be a logic 1
during reset, idle (no data), or when the transmitter is
disabled. During the local Loopback mode, the RXn
input pin is disabled and TX data is connected to the
UART RX input internally.
Receive Ready (active LOW).
RXRDY contains the
wire-ORed status of all four receive channel FIFOs,
RXRDYA to RXRDYD. A logic 0 indicates receive data
ready status, that is, the RHR is full, or the FIFO has
one or more RX characters available for unloading.
This pin goes to a logic 1 when the FIFO/RHR is empty,
or when there are no more characters available in
either the FIFO or RHR. Individual channel RX status is
read by examining individual internal registers via CS
and A0 to A4 pin functions. The RXRDY pin is not
available on the HVQFN48 package.
R/W
18
-
-
7
I
RXA
RXB
RXC
RXD
7
29
41
63
62
20
29
51
17
44
57
4
48
13
22
38
I
I
I
I
RXRDY
38
-
54
-
O
Table 2.
Symbol
Pin description
…continued
Pin
PLCC68
Type
Description
LQFP64
LQFP80 HVQFN48
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