参数资料
型号: SC16C750BIBS,151
厂商: NXP Semiconductors
文件页数: 16/44页
文件大小: 0K
描述: IC UART SINGLE W/FIFO 32-HVQFN
产品培训模块: Stand-Alone UARTs
标准包装: 490
通道数: 1,UART
FIFO's: 64 字节
电源电压: 2.5V,3.3V,5V
带自动流量控制功能:
带故障启动位检测功能:
带调制解调器控制功能:
带CMOS:
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘
供应商设备封装: 32-HVQFN(5x5)
包装: 托盘
产品目录页面: 828 (CN2011-ZH PDF)
其它名称: 568-3285
935276388151
SC16C750BIBS-S
SC16C750B_5
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 17 October 2008
23 of 44
NXP Semiconductors
SC16C750B
5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs
7.6 Modem Control Register (MCR)
This register controls the interface with the modem or a peripheral device.
The ow control can be congured by programming MCR[1] and MCR[5] as shown in
Table 18.
Modem Control Register bits description
Bit
Symbol
Description
7
MCR[7]
reserved; set to 0
6
MCR[6]
reserved; set to 0
5
MCR[5]
AFE. This bit is the auto ow control enable. When this bit is set, the auto
ow control is enabled.
4
MCR[4]
Loopback. Enable the local Loopback mode (diagnostics). In this mode the
transmitter output (TX) and the receiver input (RX), CTS, DSR, DCD, and RI
are disconnected from the SC16C750B I/O pins. Internally the modem data
and control pins are connected into a loopback data conguration (see
Figure 6). In this mode, the receiver and transmitter interrupts remain fully
operational. The Modem Control Interrupts are also operational, but the
interrupts’ sources are switched to the lower four bits of the Modem Control.
Interrupts continue to be controlled by the IER register.
logic 0 = disable Loopback mode (normal default condition)
logic 1 = enable local Loopback mode (diagnostics)
3
MCR[3]
OUT2, INT enable. Used to control the modem DCD signal in the Loopback
mode.
logic 0 = set OUT2 to HIGH. In the Loopback mode, sets OUT2 (DCD)
internally to a logic 1.
logic 1 = set OUT2 to LOW. In the Loopback mode, sets OUT2 (DCD)
internally to a logic 0.
2
MCR[2]
OUT1. This bit is used in the Loopback mode only. In the Loopback mode,
this bit is used to write the state of the modem RI interface signal via OUT1.
1
MCR[1]
RTS
logic 0 = force RTS output to a logic 1 (normal default condition)
logic 1 = force RTS output to a logic 0
0
MCR[0]
DTR
logic 0 = force DTR output to a logic 1 (normal default condition)
logic 1 = force DTR output to a logic 0
Table 19.
Flow control conguration
MCR[5] (AFE)
MCR[1] (RTS)
Flow conguration
1
auto RTS and CTS enabled
1
0
auto CTS only enabled
0
X
auto RTS and CTS disabled
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