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| 型号： | SC16C750BIBS,151 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 8/44页 |
| 文件大小： | 0K |
| 描述： | IC UART SINGLE W/FIFO 32-HVQFN |
| 产品培训模块： | Stand-Alone UARTs |
| 标准包装： | 490 |
| 通道数： | 1，UART |
| FIFO's： | 64 字节 |
| 电源电压： | 2.5V，3.3V，5V |
| 带自动流量控制功能： | 是 |
| 带故障启动位检测功能： | 是 |
| 带调制解调器控制功能： | 是 |
| 带CMOS： | 是 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 供应商设备封装： | 32-HVQFN（5x5） |
| 包装： | 托盘 |
| 产品目录页面： | 828 (CN2011-ZH PDF) |
| 其它名称： | 568-3285 935276388151 SC16C750BIBS-S |
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SC16C750B_5
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 17 October 2008
16 of 44
NXP Semiconductors
SC16C750B
5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs
7.1 Transmit Holding Register (THR) and Receive Holding Register (RHR)
The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and
Transmit Shift Register (TSR). The status of the THR is provided in the Line Status
Register (LSR). Writing to the THR transfers the contents of the data bus (D7 to D0) to the
THR, providing that the THR or TSR is empty. The THR empty ag in the LSR register will
be set to a logic 1 when the transmitter is empty or when data is transferred to the TSR.
Note that a write operation can be performed when the THR empty ag is set
(logic 0 = FIFO full; logic 1 = at least one FIFO location available).
The serial receive section also contains an 8-bit Receive Holding Register (RHR).
Receive data is removed from the SC16C750B and receive FIFO by reading the RHR
register. The receive section provides a mechanism to prevent false starts. On the falling
edge of a start or false start bit, an internal receiver counter starts counting clocks at the
16
× clock rate. After 71
2 clocks, the start bit time should be shifted to the center of the
start bit. At this time the start bit is sampled, and if it is still a logic 0 it is validated.
Evaluating the start bit in this manner prevents the receiver from assembling a false
character. Receiver status codes will be posted in the LSR.
7.2 Interrupt Enable Register (IER)
The Interrupt Enable Register (IER) masks the interrupts from receiver ready, transmitter
empty, line status and modem status registers. These interrupts would normally be seen
on the INT output pin.
Table 9.
Interrupt Enable Register bits description
Bit
Symbol
Description
7:6
IER[7:6]
Not used.
5
IER[5]
Low power mode.
logic 0 = disable Low power mode (normal default condition)
logic 1 = enable Low power mode
4
IER[4]
Sleep mode.
logic 0 = disable Sleep mode (normal default condition)
logic 1 = enable Sleep mode. See Section 6.7 “Sleep mode” for details.
3
IER[3]
Modem Status Interrupt.
logic 0 = disable the modem status register interrupt (normal default
condition)
logic 1 = enable the modem status register interrupt
2
IER[2]
Receive Line Status interrupt. This interrupt will be issued whenever a fully
assembled receive character is transferred from RSR to the RHR/FIFO, i.e.,
data ready, LSR[0].
logic 0 = disable the receiver line status interrupt (normal default condition)
logic 1 = enable the receiver line status interrupt
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SC16C750BIBS-F | 功能描述:UART 接口集成电路 16CB 2.5V-5V 1CH UART 64B FIFO RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| SC16C750BIBS-S | 制造商:NXP Semiconductors 功能描述:UART 1-CH 64Byte FIFO 2.5V/3.3V/5V 32-Pin HVQFN EP Tray |
| SC16C750IA44 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Universal Asynchronous Receiver/Transmitter (UART) with 64-byte FIFO |
| SC16C750IA44,512 | 功能描述:UART 接口集成电路 16C 2.5V-5V 1CH UART 64B FIFO RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| SC16C750IA44,518 | 功能描述:UART 接口集成电路 16C 2.5V-5V 1CH UART 64B FIFO RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
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