参数资料
型号: SC16C752BIB48,151
厂商: NXP Semiconductors
文件页数: 5/47页
文件大小: 0K
描述: IC DUAL UART 64BYTE 48LQFP
标准包装: 250
通道数: 2,DUART
FIFO's: 64 字节
电源电压: 2.5V,3.3V,5V
带自动流量控制功能:
带故障启动位检测功能:
带调制解调器控制功能:
安装类型: 表面贴装
封装/外壳: 48-LQFP
供应商设备封装: 48-LQFP(7x7)
包装: 托盘
其它名称: 935274411151
SC16C752BIB48-S
SC16C752BIB48-S-ND
SC16C752B
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 6 — 30 November 2010
13 of 47
NXP Semiconductors
SC16C752B
5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
6.5 Interrupts
The SC16C752B has interrupt generation and prioritization (six prioritized levels of
interrupts) capability. The Interrupt Enable Register (IER) enables each of the six types of
interrupts and the INTA/INTB signal in response to an interrupt generation. The IER can
also disable the interrupt system by clearing bit 0 to bit 3 and bit 5 to bit 7. When an
interrupt is generated, the IIR indicates that an interrupt is pending and provides the type
of interrupt through IIR[5:0]. Table 6 summarizes the interrupt control functions.
It is important to note that for the framing error, parity error, and break conditions, LSR[7]
generates the interrupt. LSR[7] is set when there is an error anywhere in the RX FIFO,
and is cleared only when there are no more errors remaining in the FIFO. LSR[4:2] always
represent the error status for the received character at the top of the RX FIFO. Reading
the RX FIFO updates LSR[4:2] to the appropriate status for the new character at the top of
the FIFO. If the RX FIFO is empty, then LSR[4:2] are all zeros.
For the Xoff interrupt, if an Xoff flow character detection caused the interrupt, the interrupt
is cleared by an Xon flow character detection. If a special character detection caused the
interrupt, the interrupt is cleared by a read of the LSR.
Table 6.
Interrupt control functions
IIR[5:0]
Priority
level
Interrupt type
Interrupt source
Interrupt reset method
00 0001
None
none
00 0110
1
receiver line status
OE, FE, PE, or BI errors occur in
characters in the RX FIFO
FE, PE, BI: all erroneous
characters are read from the
RX FIFO.
OE: read LSR
00 1100
2
RX time-out
stale data in RX FIFO
read RHR
00 0100
2
RHR interrupt
DRDY (data ready)
(FIFO disable)
RX FIFO above trigger level
(FIFO enable)
read RHR
00 0010
3
THR interrupt
TFE (THR empty)
(FIFO disable)
TX FIFO passes above trigger level
(FIFO enable)
read IIR or a write to the THR
00 0000
4
modem status
MSR[3:0] = logic 0
read MSR
01 0000
5
Xoff interrupt
receive Xoff character(s)/special
character
receive Xon character(s)/Read of
IIR
10 0000
6
CTS, RTS
RTSn pin or CTSn pin change state
from active (LOW) to inactive (HIGH)
read IIR
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SC16C752BIB48-S 功能描述:UART 接口集成电路 16CB 2.5V-5V 2CH UART 64B FIFO RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel
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