参数资料
| 型号： | SC16C752BIBS,128 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 17/47页 |
| 文件大小： | 0K |
| 描述： | IC DUAL UART 64BYTE 32HVQFN |
| 标准包装： | 6,000 |
| 通道数： | 2，DUART |
| FIFO's： | 64 字节 |
| 电源电压： | 2.5V，3.3V，5V |
| 带自动流量控制功能： | 是 |
| 带故障启动位检测功能： | 是 |
| 带调制解调器控制功能： | 是 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 供应商设备封装： | 32-HVQFN（5x5） |
| 包装： | 带卷 (TR) |
| 其它名称： | 935276389128 SC16C752BIBS-F SC16C752BIBS-F-ND |
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SC16C752B
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 6 — 30 November 2010
24 of 47
NXP Semiconductors
SC16C752B
5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
7.5 Line Status Register (LSR)
Table 13 shows the Line Status Register bit settings.
When the LSR is read, LSR[4:2] reflect the error bits (BI, FE, PE) of the character at the
top of the receive FIFO (next character to be read). The LSR[4:2] registers do not
physically exist, as the data read from the receive FIFO is output directly onto the output
data bus, DI[4:2], when the LSR is read. Therefore, errors in a character are identified by
reading the LSR and then reading the RHR.
LSR[7] is set when there is an error anywhere in the receive FIFO, and is cleared only
when there are no more errors remaining in the FIFO.
Reading the LSR does not cause an increment of the receive FIFO read pointer. The
receive FIFO read pointer is incremented by reading the RHR.
Table 13.
Line Status Register bits description
Bit
Symbol
Description
7
LSR[7]
FIFO data error.
logic 0 = no error (normal default condition)
logic 1 = At least one parity error, framing error, or break indication is in the
receiver FIFO. This bit is cleared when no more errors are present in the
FIFO.
6
LSR[6]
THR and TSR empty. This bit is the Transmit Empty indicator.
logic 0 = transmitter hold and shift registers are not empty
logic 1 = transmitter hold and shift registers are empty
5
LSR[5]
THR empty. This bit is the Transmit Holding Register Empty indicator.
logic 0 = Transmit Holding Register is not empty
logic 1 = Transmit Holding Register is empty. The processor can now load
up to 64 bytes of data into the THR if the transmit FIFO is enabled.
4
LSR[4]
Break interrupt.
logic 0 = No break condition (normal default condition)
logic 1 = A break condition occurred and associated byte is 00, i.e.,
RXn was LOW for one character time frame
3
LSR[3]
Framing error.
logic 0 = no framing error in data being read from receive FIFO (normal
default condition)
logic 1 = framing error occurred in data being read from receive FIFO, i.e.,
received data did not have a valid stop bit.
2
LSR[2]
Parity error.
logic 0 = no parity error (normal default condition)
logic 1 = parity error in data being read from receive FIFO
1
LSR[1]
Overrun error.
logic 0 = no overrun error (normal default condition)
logic 1 = overrun error has occurred
0
LSR[0]
Data in receiver.
logic 0 = no data in receive FIFO (normal default condition)
logic 1 = at least one character in the receive FIFO
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SC16C752BIBS-F | 功能描述:UART 接口集成电路 16CB 2.5V-5V 2CH UART 64B FIFO RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| SC16C752BIBS-S | 功能描述:UART 接口集成电路 2CH. UART 64B FIFO RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| SC16C752IB48 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Dual UART with 64-byte FIFO |
| SC16C752IB48,128 | 功能描述:UART 接口集成电路 Dual UART 64-byte FIFO RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| SC16C752IB48,151 | 功能描述:UART 接口集成电路 16C 2.5V-5V 2CH UART 64B FIFO RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
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