SC16C752B
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NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 6 — 30 November 2010
5 of 47
NXP Semiconductors
SC16C752B
5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Type
Description
LQFP48 HVQFN32
A0
28
19
I
Address 0 select bit. Internal registers address selection.
A1
27
18
I
Address 1 select bit. Internal registers address selection.
A2
26
17
I
Address 2 select bit. Internal registers address selection.
CDA
40
-
I
Carrier Detect (active LOW). These inputs are associated with individual
UART channels A and B. A logic LOW on these pins indicates that a carrier has
been detected by the modem for that channel. The state of these inputs is
reflected in the Modem Status Register (MSR).
CDB
16
-
i
CSA
10
8
I
Chip Select (active LOW). These pins enable data transfers between the user
CPU and the SC16C752B for the channel(s) addressed. Individual UART
sections (A, B) are addressed by providing a logic LOW on the respective CSA
and CSB pins.
CSB
11
9
I
CTSA
38
25
I
Clear to Send (active LOW). These inputs are associated with individual UART
channels A and B. A logic 0 (LOW) on the CTSn pins indicates the modem or
data set is ready to accept transmit data from the SC16C752B. Status can be
tested by reading MSR[4]. These pins only affect the transmit and receive
operations when auto-CTS function is enabled via the Enhanced Feature
Register EFR[7] for hardware flow control operation.
CTSB
23
16
I
D0
44
27
I/O
Data bus (bidirectional). These pins are the 8-bit, 3-state data bus for
transferring information to or from the controlling CPU. D0 is the least significant
bit and the first data bit in a transmit or receive serial data stream.
D1
45
28
I/O
D2
46
29
I/O
D3
47
30
I/O
D4
48
31
I/O
D5
1
32
I/O
D6
2
1
I/O
D7
3
2
I/O
DSRA
39
-
I
Data Set Ready (active LOW). These inputs are associated with individual
UART channels A and B. A logic 0 (LOW) on these pins indicates the modem or
data set is powered-on and is ready for data exchange with the UART. The state
of these inputs is reflected in the Modem Status Register (MSR).
DSRB
20
-
I
DTRA
34
-
O
Data Terminal Ready (active LOW). These outputs are associated with
individual UART channels A and B. A logic 0 (LOW) on these pins indicates that
the SC16C752B is powered-on and ready. These pins can be controlled via the
modem control register. Writing a logic 1 to MCR[0] will set the DTRn output to
logic 0 (LOW), enabling the modem. The output of these pins will be a logic 1
after writing a logic 0 to MCR[0], or after a reset.
DTRB
35
-
O
GND
17
13
I
Signal and power ground
INTA
30
21
O
Interrupt A and B (active HIGH). These pins provide individual channel
interrupts INTA and INTB. INTA and INTB are enabled when MCR[3] is set to a
logic 1, interrupt sources are enabled in the Interrupt Enable Register (IER).
Interrupt conditions include: receiver errors, available receiver buffer data,
available transmit buffer space, or when a modem status flag is detected. INTA,
INTB are in the high-impedance state after reset.
INTB
29
20
O
IOR
19
14
I
Input/Output Read strobe (active LOW). A HIGH-to-LOW transition on IOR
will load the contents of an internal register defined by address bits A0 to A2
onto the SC16C752B data bus (D0 to D7) for access by external CPU.