参数资料
型号: SC16C752IB48,151
厂商: NXP Semiconductors
文件页数: 10/47页
文件大小: 0K
描述: IC UART DUAL W/FIFO 48-LQFP
标准包装: 250
通道数: 2,DUART
FIFO's: 64 字节
电源电压: 2.5V,3.3V,5V
带自动流量控制功能:
带故障启动位检测功能:
带调制解调器控制功能:
安装类型: 表面贴装
封装/外壳: 48-LQFP
供应商设备封装: 48-LQFP(7x7)
包装: 托盘
其它名称: 568-3289
935270055151
SC16C752IB48-S
Philips Semiconductors
SC16C752
Dual UART with 64-byte FIFO
Product data
Rev. 04 — 20 June 2003
18 of 47
9397 750 11635
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
7.
Register descriptions
Each register is selected using address lines A0, A1, A2, and in some cases, bits
from other registers. The programming combinations for register selection are shown
[1]
MCR[7] can only be modied when EFR[4] is set.
[2]
Accessed by a combination of address pins and register bits.
[3]
Accessible only when LCR[7] is logic 1.
[4]
Accessible only when LCR is set to 10111111 (8hBF).
[5]
Accessible only when EFR[4] = 1 and MCR[6] = 1, i.e., EFR[4] and MCR[6] are read/write enables.
[6]
Accessible only when CSA or CSB = 0, MCR[2] = 1, and loop-back is disabled (MCR[4] = 0).
Fig 12. Crystal oscillator connections.
002aaa169
X1
1.8432 MHz
C1
22 pF
C2
47 pF
XT
AL1
XT
AL2
X1
1.8432 MHz
C1
47 pF
C2
100 pF
XT
AL1
XT
AL2
1.5 k
Table 9:
Register map - read/write properties
A2
A1
A0
Read mode
Write mode
0
receive holding register (RHR)
transmit holding register (THR)
0
1
interrupt enable register (IER)
interrupt enable register
0
1
0
interrupt identication register (IIR)
FIFO control register (FCR)
0
1
line control register (LCR)
line control register
1
0
modem control register (MCR)[1]
modem control register[1]
1
0
1
line status register (LSR)
1
0
modem status register (MSR)
1
scratchpad register (SPR)
scratchpad register
0
divisor latch LSB (DLL)[2], [3]
divisor latch LSB[2], [3]
0
1
divisor latch MSB (DLH)[2], [3]
divisor latch MSB[2], [3]
0
1
0
enhanced feature register (EFR)[2], [4]
enhanced feature register[2], [4]
1
0
1
0
1
1
0
1
1
0
transmission control register (TCR)[2], [5] transmission control register[2], [5]
1
trigger level register (TLR)[2], [5]
trigger level register[2], [5]
1
FIFO ready register[2], [6]
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