参数资料
型号: SC16C754BIB80,551
厂商: NXP Semiconductors
文件页数: 14/50页
文件大小: 0K
描述: IC UART QUAD 64BYTE 80LQFP
标准包装: 119
通道数: 4,QUART
FIFO's: 64 字节
电源电压: 2.5V,3.3V,5V
带自动流量控制功能:
带故障启动位检测功能:
带调制解调器控制功能:
安装类型: 表面贴装
封装/外壳: 80-LQFP
供应商设备封装: 80-LQFP(12x12)
包装: 托盘
其它名称: 935274939551
SC16C754BIB80-S
SC16C754BIB80-S-ND
SC16C754B_4
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 6 October 2008
21 of 51
NXP Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
7.
Register descriptions
Each register is selected using address lines A0, A1, A2, and in some cases, bits from
other registers. The programming combinations for register selection are shown in
[1]
MCR[7] can only be modied when EFR[4] is set.
[2]
Accessed by a combination of address pins and register bits.
[3]
Accessible only when LCR[7] is logic 1.
[4]
Accessible only when LCR is set to 1011 1111 (BFh).
[5]
Accessible only when EFR[4] = 1 and MCR[6] = 1, that is, EFR[4] and MCR[6] are read/write enables.
[6]
Accessible only when CSA to CSD = 0, MCR[2] = 1, and loopback is disabled (MCR[4] = 0).
Fig 14. Crystal oscillator connection
002aaa870
C2
47 pF
XTAL1
XTAL2
X1
1.8432 MHz
C1
22 pF
C2
33 pF
XTAL1
XTAL2
1.5 k
X1
1.8432 MHz
C1
22 pF
Table 9.
Register map - read/write properties
A2
A1
A0
Read mode
Write mode
0
Receive Holding Register (RHR)
Transmit Holding Register (THR)
0
1
Interrupt Enable Register (IER)
0
1
0
Interrupt Identication Register (IIR)
FIFO Control Register (FCR)
0
1
Line Control Register (LCR)
1
0
Modem Control Register (MCR)[1]
Modem Control Register (MCR)[1]
1
0
1
Line Status Register (LSR)
not applicable
1
0
Modem Status Register (MSR)
not applicable
1
ScratchPad Register (SPR)
0
Divisor Latch LSB (DLL)[2][3]
Divisor Latch LSB (DLL)[2][3]
0
1
Divisor Latch MSB (DLM)[2][3]
0
1
0
Enhanced Feature Register (EFR)[2][4]
Enhanced Feature Register (EFR)[2][4]
1
0
Xon1 word[2][4]
1
0
1
Xon2 word[2][4]
1
0
Xoff1 word[2][4]
1
Xoff2 word[2][4]
1
0
Transmission Control Register
(TCR)[2][5]
Transmission Control Register
1
Trigger Level Register (TLR)[2][5]
Trigger Level Register (TLR)[2][5]
1
FIFO ready register[2][6]
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