参数资料
型号: SC16C754BIB80,551
厂商: NXP Semiconductors
文件页数: 4/50页
文件大小: 0K
描述: IC UART QUAD 64BYTE 80LQFP
标准包装: 119
通道数: 4,QUART
FIFO's: 64 字节
电源电压: 2.5V,3.3V,5V
带自动流量控制功能:
带故障启动位检测功能:
带调制解调器控制功能:
安装类型: 表面贴装
封装/外壳: 80-LQFP
供应商设备封装: 80-LQFP(12x12)
包装: 托盘
其它名称: 935274939551
SC16C754BIB80-S
SC16C754BIB80-S-ND
SC16C754B_4
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 6 October 2008
12 of 51
NXP Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
6.3 Software ow control
Software ow control is enabled through the enhanced feature register and the modem
control register. Different combinations of software ow control can be enabled by setting
different combinations of EFR[3:0]. Table 3 shows software ow control options.
Remark: When using software ow control, the Xon/Xoff characters cannot be used for
data characters.
There are two other enhanced features relating to software ow control:
‘Xon Any’ function (MCR[5]): Operation will resume after receiving any character
after recognizing the Xoff character. It is possible that an Xon1 character is
recognized as an ‘Xon Any’ character, which could cause an Xon2 character to be
written to the RX FIFO.
Special character (EFR[5]): Incoming data is compared to Xoff2. Detection of the
special character sets the Xoff interrupt (IIR[4]) but does not halt transmission. The
Xoff interrupt is cleared by a read of the IIR. The special character is transferred to the
RX FIFO.
6.3.1 RX
When software ow control operation is enabled, the SC16C754B will compare incoming
data with Xoff1/Xoff2 programmed characters (in certain cases, Xoff1 and Xoff2 must be
received sequentially). When the correct Xoff character is received, transmission is halted
after completing transmission of the current character. Xoff detection also sets IIR[4] (if
enabled via IER[5]) and causes INT to go HIGH.
To resume transmission, an Xon1/Xon2 character must be received (in certain cases
Xon1 and Xon2 must be received sequentially). When the correct Xon characters are
received, IIR[4] is cleared, and the Xoff interrupt disappears.
Table 3.
Software ow control options (EFR[3:0])
EFR[3]
EFR[2]
EFR[1]
EFR[0]
TX, RX software ow controls
0
X
no transmit ow control
1
0
X
transmit Xon1, Xoff1
0
1
X
transmit Xon2, Xoff2
1
X
transmit Xon1, Xon2, Xoff1, Xoff2
X
0
no receive ow control
X
1
0
receiver compares Xon1, Xoff1
X
0
1
receiver compares Xon2, Xoff2
1
0
1
transmit Xon1, Xoff1
receiver compares Xon1 or Xon2, Xoff1 or Xoff2
0
1
transmit Xon2, Xoff2
receiver compares Xon1 or Xon2, Xoff1 or Xoff2
1
transmit Xon1, Xon2, Xoff1, Xoff2
receiver compares Xon1 and Xon2, Xoff1 and Xoff2
0
1
no transmit ow control
receiver compares Xon1 and Xon2, Xoff1 and Xoff2
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