参数资料
型号: SC16C850IBS,151
厂商: NXP Semiconductors
文件页数: 30/55页
文件大小: 0K
描述: IC UART SGL-CH 3.3V 32-HVQFN
标准包装: 490
特点: 可编程
通道数: 1,UART
FIFO's: 128 字节
规程: RS485
电源电压: 2.5 V ~ 3.3 V
带自动流量控制功能:
带IrDA 编码器/解码器:
带故障启动位检测功能:
带调制解调器控制功能:
带CMOS:
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘
供应商设备封装: 32-HVQFN(5x5)
包装: 托盘
产品目录页面: 828 (CN2011-ZH PDF)
其它名称: 568-4778
935283103151
SC16C850
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 11 November 2010
36 of 55
NXP Semiconductors
SC16C850
2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder
7.22 Advanced Feature Control Register 1 (AFCR1)
[1]
It takes 4 XTAL1 clocks to reset the device.
Table 32.
Advanced Feature Control Register 1 register bits description
Bit
Symbol
Description
7:5
AFCR1[7:5]
reserved
4
AFCR1[4]
Sleep RXLow. Program RX input to be edge-sensitive or level-sensitive.
logic 0 = RX input is level-sensitive. If RX pin is LOW, the UART will
not go to sleep. Once the UART is in Sleep mode, it will wake up if RX
pin goes LOW.
logic 1 = RX input is edge-sensitive. UART will go to sleep even if RX
pin is LOW, and will wake up when RX pin toggles.
3
AFCR1[3]
reserved
2
AFCR1[2]
RTS/CTS mapped to DTR/DSR. Switch the function of RTS/CTS to
DTR/DSR.
logic 0 = RTS and CTS signals are used for hardware flow control.
logic 1 = DTR and DSR signals are used for hardware flow control.
RTS and CTS retain their functionality.
1
AFCR1[1]
SReset. Software Reset. A write to this bit will reset the UART. Once the
UART is reset this bit is automatically set to 0.[1]
0
AFCR1[0]
TSR Interrupt. Select TSR interrupt mode
logic 0 = transmit empty interrupt occurs when transmit FIFO falls
below the trigger level or becomes empty.
logic 1 = transmit empty interrupt occurs when transmit FIFO falls
below the trigger level, or becomes empty and the last stop bit has
been shifted out of the Transmit Shift Register.
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