参数资料
型号: SC16IS752IPW-S
厂商: NXP Semiconductors
文件页数: 17/60页
文件大小: 0K
描述: IC UART DUAL I2C/SPI 28-TSSOP
产品培训模块: Bridge Solutions
标准包装: 63
特点: 低电流
通道数: 2,DUART
FIFO's: 64 字节
规程: RS232,RS485
电源电压: 2.5V, 3.3V
带自动流量控制功能:
带IrDA 编码器/解码器:
带故障启动位检测功能:
带调制解调器控制功能:
安装类型: 表面贴装
封装/外壳: 28-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 28-TSSOP
包装: 管件
配用: 568-4000-ND - DEMO BOARD SPI/I2C TO DUAL UART
568-3510-ND - DEMO BOARD SPI/I2C TO UART
其它名称: 568-2237
SC16IS752_SC16IS762
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 9 — 22 March 2012
24 of 60
NXP Semiconductors
SC16IS752; SC16IS762
Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
8.5 Interrupt Identification Register (IIR)
The IIR is a read-only 8-bit register which provides the source of the interrupt in a
prioritized manner. Table 13 shows Interrupt Identification Register bit settings.
[1]
Modem interrupt status must be read via MSR register and GPIO interrupt status must be read via IOState
register.
8.6 Line Control Register (LCR)
This register controls the data communication format. The word length, number of stop
bits, and parity type are selected by writing the appropriate bits to the LCR. Table 15
shows the Line Control Register bit settings.
Table 13.
Interrupt Identification Register bits description
Bit
Symbol
Description
7:6
IIR[7:6]
Mirror the contents of FCR[0].
5:1
IIR[5:1]
5-bit encoded interrupt. See Table 14.
0
IIR[0]
Interrupt status.
logic 0 = an interrupt is pending
logic 1 = no interrupt is pending
Table 14.
Interrupt source
Priority
level
IIR[5]
IIR[4]
IIR[3]
IIR[2]
IIR[1]
IIR[0]
Source of the interrupt
1
000
11
0Receive Line Status error
2
0
1
0
Receiver time-out interrupt
2
0
1
0
RHR interrupt
3
000
01
0THR interrupt
4
000
00
0modem interrupt[1]
5
1
0
input pin change of state[1]
6
0
1
0
received Xoff signal/special
character
7
100
00
0CTS, RTS change of state
from active (LOW) to
inactive (HIGH)
Table 15.
Line Control Register bits description
Bit
Symbol
Description
7
LCR[7]
Divisor latch enable.
logic 0 = divisor latch disabled (normal default condition)
logic 1 = divisor latch enabled
6
LCR[6]
Break control bit. When enabled, the Break control bit causes a break
condition to be transmitted (the TX output is forced to a logic 0 state).
This condition exists until disabled by setting LCR[6] to a logic 0.
logic 0 = no TX break condition (normal default condition)
logic 1 = forces the transmitter output (TX) to a logic 0 to alert the
communication terminal to a line break condition
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