参数资料
型号: SC16IS752IPW-S
厂商: NXP Semiconductors
文件页数: 20/60页
文件大小: 0K
描述: IC UART DUAL I2C/SPI 28-TSSOP
产品培训模块: Bridge Solutions
标准包装: 63
特点: 低电流
通道数: 2,DUART
FIFO's: 64 字节
规程: RS232,RS485
电源电压: 2.5V, 3.3V
带自动流量控制功能:
带IrDA 编码器/解码器:
带故障启动位检测功能:
带调制解调器控制功能:
安装类型: 表面贴装
封装/外壳: 28-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 28-TSSOP
包装: 管件
配用: 568-4000-ND - DEMO BOARD SPI/I2C TO DUAL UART
568-3510-ND - DEMO BOARD SPI/I2C TO UART
其它名称: 568-2237
SC16IS752_SC16IS762
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 9 — 22 March 2012
27 of 60
NXP Semiconductors
SC16IS752; SC16IS762
Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
8.8 Line Status Register (LSR)
Table 20 shows the Line Status Register bit settings.
When the LSR is read, LSR[4:2] reflect the error bits (BI, FE, PE) of the character at the
top of the RX FIFO (next character to be read). Therefore, errors in a character are
identified by reading the LSR and then reading the RHR.
LSR[7] is set when there is an error anywhere in the RX FIFO, and is cleared only when
there are no more errors remaining in the FIFO.
Table 20.
Line Status Register bits description
Bit
Symbol
Description
7
LSR[7]
FIFO data error.
logic 0 = no error (normal default condition)
logic 1 = at least one parity error, framing error, or break indication is in
the receiver FIFO. This bit is cleared when no more errors are present
in the FIFO.
6
LSR[6]
THR and TSR empty. This bit is the Transmit Empty indicator.
logic 0 = transmitter hold and shift registers are not empty
logic 1 = transmitter hold and shift registers are empty
5
LSR[5]
THR empty. This bit is the Transmit Holding Register Empty indicator.
logic 0 = Transmit Hold Register is not empty.
logic 1 = Transmit Hold Register is empty. The host can now load up to
64 characters of data into the THR if the TX FIFO is enabled.
4
LSR[4]
Break interrupt.
logic 0 = no break condition (normal default condition).
logic 1 = a break condition occurred and associated character is 0x00
(RX was LOW for one character time frame)
3
LSR[3]
Framing error.
logic 0 = no framing error in data being read from RX FIFO (normal
default condition)
logic 1 = framing error occurred in data being read from RX FIFO
(received data did not have a valid stop bit)
2LSR[2]
Parity error.
logic 0 = no parity error (normal default condition)
logic 1 = parity error in data being read from RX FIFO
1
LSR[1]
Overrun error.
logic 0 = no overrun error (normal default condition)
logic 1 = overrun error has occurred
0
LSR[0]
Data in receiver.
logic 0 = no data in receive FIFO (normal default condition)
logic 1 = at least one character in the RX FIFO
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