参数资料
型号: SC16IS752IPW-T
厂商: NXP Semiconductors
文件页数: 44/60页
文件大小: 0K
描述: IC UART DUAL I2C/SPI 28-TSSOP
标准包装: 2,500
特点: 低电流
通道数: 2,DUART
FIFO's: 64 字节
规程: RS232,RS485
电源电压: 2.5V, 3.3V
带自动流量控制功能:
带IrDA 编码器/解码器:
带故障启动位检测功能:
带调制解调器控制功能:
安装类型: 表面贴装
封装/外壳: 28-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 28-TSSOP
包装: 带卷 (TR)
配用: 568-4000-ND - DEMO BOARD SPI/I2C TO DUAL UART
568-3510-ND - DEMO BOARD SPI/I2C TO UART
SC16IS752_SC16IS762
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 9 — 22 March 2012
49 of 60
NXP Semiconductors
SC16IS752; SC16IS762
Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
Table 39.
SPI-bus timing specifications
All the timing limits are valid within the operating supply voltage, ambient temperature range and output load;
VDD =2.5 V 0.2 V, Tamb = 40 Cto+85 C; or VDD =3.3 V 0.3 V, Tamb = 40 Cto +95 C; VIL and VIH refer to input
voltage of VSS to VDD. All output load = 25 pF, unless otherwise specified.
Symbol
Parameter
Conditions
VDD =2.5 V
VDD =3.3 V
Unit
Min
Max
Min
Max
tTR
CS HIGH to SO 3-state
CL = 100 pF
-
100
-
100
ns
tCSS
CS to SCLK setup time
100
-
100
-
ns
tCSH
CS to SCLK hold time
5
-
5
-
ns
tDO
SCLK fall to SO valid delay time
CL = 100 pF
-
25
-
20
ns
tDS
SI to SCLK setup time
10
-
10
-
ns
tDH
SI to SCLK hold time
10
-
10
-
ns
tCP
SCLK period
tCL + tCH
83
-
67
-
ns
tCH
SCLK HIGH time
30
-
25
-
ns
tCL
SCLK LOW time
30
-
25
-
ns
tCSW
CS HIGH pulse width
200
-
200
-
ns
td9
SPI output data valid time
200
-
200
-
ns
td10
SPI modem output data valid time
200
-
200
-
ns
td11
SPI transmit interrupt clear time
200
-
200
-
ns
td12
SPI modem input interrupt clear time
200
-
200
-
ns
td13
SPI interrupt clear time
200
-
200
-
ns
td14
SPI receive interrupt clear time
200
-
200
-
ns
tw(rst)
reset pulse width
3
-
3
-
s
Fig 30. Detailed SPI-bus timing
tCSH
tCSS
tCL
tCH
tCSH
tDO
tTR
tDS
tDH
SO
SI
SCLK
CS
002aab066
tCSW
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