参数资料
| 型号： | SC2443MLTRT |
| 厂商： | Semtech |
| 文件页数： | 13/22页 |
| 文件大小： | 0K |
| 描述： | IC DUAL SYNC STP-DN CTRLR 24MLPQ |
| 标准包装： | 1 |
| 应用： | 控制器，DDR |
| 输入电压： | 4.75 V ~ 16 V |
| 输出数： | 2 |
| 输出电压： | 可调至 0.5V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-MLPQ |
| 供应商设备封装： | 24-MLPQ（4x4） |
| 包装： | 标准包装 |
| 产品目录页面： | 1358 (CN2011-ZH PDF) |
| 其它名称： | SC2443MLDKR |
SC2443
Applications Information (continued)
R o 2 =
R o 1 .
very high switching frequency and very short duty cycle
is not practical. If the voltage conversion ratio VO / VIN
and hence the required duty cycle is higher, the switching
frequency can be increased to reduce the sizes of passive
components.
There will not be enough modulation headroom if the
on time is simply made equal to the minimum on time
of the SC2443. For ease of control, we recommend the
required pulse width to be at least .5 times the minimum
on time.
Setting the Switching Frequency
The switching frequency is set with an external resistor
connected from Pin 24 to ground. The set frequency is
inversely proportional to the resistor value (Figure 2).
Figure 2. Free running frequency vs. ROSC.
800
700
600
500
400
300
200
100
0
0 50 100 150 200 250
Rosc (k Ohm)
Setting the Output Voltage
The non-inverting input of the channel-one error amplifier
is internally tied the 0.5V voltage reference output (Pin 5).
The non-inverting input of the channel-two error amplifier
is brought out as a device pin (Pin 6) to which the user can
connect Pin 5 or an external voltage reference. A simple
voltage divider (Ro at top and Ro2 at bottom) sets the
converter output voltage. The voltage feedback gain
h=0.5/Vo is related to the divider resistors value as
h
1 - h
PC Board Layout Issues
Circuit board layout is very important for the proper
operation of high frequency switching power converters.
A power ground plane is required to reduce ground
bounces. The following are suggested for proper layout:
Power Stage
) Separate the power ground from the signal ground. In
the SC2443, the power ground PGND should be tied to
the source terminal of lower MOSFETs. The signal ground
AGND should be tied to the negative terminal of the
output capacitor.
2) Minimize the size of high pulse current loop. Keep the
top MOSFET, bottom MOSFET and the input capacitors
within a small area with short and wide traces. In addition
to the aluminum energy storage capacitors, add multi-
layer ceramic (MLC) capacitors from the input to the
power ground to improve high frequency bypass.
3) Reduce high frequency voltage ringing. Widen and
shorten the drain and source traces of the MOSFET to
reduce stray inductances. Add a small RC snubber if
necessary to reduce the high frequency ringing at the
phase node. Sometimes slowing down the gate drive
signal also helps in reducing the high frequency ringing
at the phase node.
4) Shorten the gate driver path. Integrity of the gate drive
(voltage level, leading and falling edges) is important for
circuit operation and efficiency. Short and wide gate drive
traces reduce trace inductances. Bond wire inductance is
about 2~3nH. If the length of the PCB trace from the gate
driver to the MOSFET gate is inch, the trace inductance
will be about 25nH. If the gate drive current is 2A with
0ns rise and falling times, the voltage drops across
the bond wire and the PCB trace will be 0.6V and 5V
respectively. This may slow down the switching transient
of the MOSFET. These inductances may also ring with the
gate capacitance.
5) Put the decoupling capacitor for the gate drive power
supplies (BST and PVCC) close to the IC and power
ground.
Control Section
6) The frequency-setting resistor Rosc should be placed
close to Pin 3. Trace length from this resistor to the analog
3
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