Circuit efficiency: ?/DIV>
Selection criteria and design procedures for the
following are described:
1) output inductor (L) type and value
2) output capacitor (C
o
) type and value
3) input capacitor (C
in
) type and value
4) power MOSFETs
5) current sensing and limiting circuit
6) voltage sensing circuit
7) loop compensation network
Operating Frequency (f
Operating Frequency (f
Operating Frequency (f
Operating Frequency (f
Operating Frequency (f
ss ss s
))
)))
The switching frequency in the SC2463 is user-
programmable. The advantages of using constant
frequency operation are simple passive component
selection and ease of feedback compensation. Before
setting the operating frequency, the following trade-offs
should be considered:
1) Passive component size
2) Circuitry efficiency
3) EMI condition
4) Minimum switch on time and
5) Maximum duty ratio
For a given output power, the sizes of the passive
components are inversely proportional to the switching
frequency, whereas MOSFET/Diode switching losses are
proportional to the operating frequency. Other issues
such as heat dissipation, packaging and the cost issues
are also to be considered. The frequency bands for
signal transmission should be avoided because of EM
interference.
Minimum Switc
Minimum Switc
Minimum Switc
Minimum Switc
Minimum Switch On Time Consideration
h On Time Consideration
h On Time Consideration
h On Time Consideration
h On Time Consideration
In the SC2463, the falling edge of the clock turns on
the top MOSFET. The inductor current and the sensed
voltage ramp up. After the internal ramp voltage crosses
a threshold determined by the error amplifier output,
the top MOSFET is turned off. The propagation delay
time from the turn-on of the controlling FET to its turn-
off is the minimum switch on time. The SC2463 has a
minimum on time of about 50ns at room temperature.
This is the shortest on interval of the controlling FET.
The controller either does not turn on the top MOSFET
at all or turns it on for at least 50ns.
For a synchronous step-down converter, the operating
duty cycle is V
O
/V
IN
. So the required on time for the top
MOSFET is V
O
/(V
IN
fs). If the frequency is set such that
the required pulse width is less than 50ns, then the
converter will start skipping cycles. Due to minimum on
time limitation, simultaneously operating at very high
switching frequency and very short duty cycle is not
practical. If the voltage conversion ratio V
O
/V
IN
and
hence the required duty cycle is higher, the switching
frequency can be increased to reduce the size of passive
components.