参数资料
| 型号： | SC28C94A1A,518 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 30/39页 |
| 文件大小： | 0K |
| 描述： | IC UART QUAD W/FIFO 52-PLCC |
| 产品培训模块： | Stand-Alone UARTs |
| 标准包装： | 1 |
| 特点： | 故障启动位检测 |
| 通道数： | 4，QUART |
| FIFO's： | 8 字节 |
| 电源电压： | 5V |
| 带自动流量控制功能： | 是 |
| 带故障启动位检测功能： | 是 |
| 带调制解调器控制功能： | 是 |
| 带CMOS： | 是 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 52-LCC（J 形引线） |
| 供应商设备封装： | 52-PLCC（19.2x19.2） |
| 包装： | 标准包装 |
| 产品目录页面： | 828 (CN2011-ZH PDF) |
| 其它名称： | 568-1114-6 |
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Philips Semiconductors
Product data sheet
SC28C94
Quad universal asynchronous receiver/transmitter (QUART)
2006 Aug 09
36
addressed register. The generation of DACKN begins with the start
of a bus cycle (Read, Write or Interrupt Acknowledge) and then
requires two edges of the X1 clock plus typically 70ns for its
assertion.
In this mode the writing of data to the QUART registers occurs on
the falling edge of DACKN or the rising edge of the combination of
CEN and WRN which ever occurs first. This requires that the data
to be written to the QUART registers be valid with respect to the
leading edge of the combination of CEN and WRN. (In the
synchronous mode it is the trailing edge)
IACKN updates the CIR (Current Interrupt Register) and places the
Interrupt Vector or Modified Interrupt Vector on the bus if the
Interrupt Vector is used.
The Synchronous Interface
In this mode the DACKN and IACKN are usually not used. Here
data is written to the QUART on the trailing edge of the
combination of CEN and WRN. The placing of data on the bus
during a read cycle begins with the leading edge of the combination
of CEN and RDN.
The read cycle will terminate with the rise of CEN or RDN which
ever one occurs first. In this mode bus cycles are usually setup to be
the minimum time required by the QUART and hence will be faster
than bus cycles that are defined by the DACKN signal. DACKN
should be turned off in this mode.
When IACKN is not used or is not available the command at 2Ah
should be used to update the CIR (Current Interrupt Register). This
register is normally updated by IACKN in response to the IRQN.
Note that the CIR is not updated by IRQN since there could be a
long time between the assertion of IRQN and the start of the
interrupt service routine. During this time it is quite possible that
another interrupt with a higher priority occurs. It is the CIR that
contains the information that describes the interrupt source and its
priority. It is therefor recommended that the first operation upon
entering the interrupt service routine is the updating of the CIR.
(Recall that the contents of the GLOBAL registers reflect the content
of the CIR)
Summary
In the asynchronous mode all of the interface pins are usually used.
The synchronous mode usually will not use the IACKN and DACKN.
However there is no conflict in the quart if both modes are used in
the same application. (i.e. More than one device may control the
QUART) The principles to keep in mind are:
1. When IACKN is not used the CIR should be updated via
command.
2. If DACKN is not used it should be disabled.
3. When in the asynchronous mode be sure DACKN is enabled.
4. With 68xxx type controllers the RDN signal must be generated.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SC28C94A1AB | 制造商:PHILIPS-SEMI 功能描述: |
| SC28C94A1N | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Quad universal asynchronous receiver/transmitter QUART |
| SC28C94A1N,112 | 功能描述:IC UART QUAD W/FIFO 48-DIP RoHS:是 类别:集成电路 (IC) >> 接口 - UART（通用异步接收器/发送器） 系列:- 标准包装:250 系列:- 特点:* 通道数:2，DUART FIFO's:16 字节 规程:RS232，RS485 电源电压:2.25 V ~ 5.5 V 带并行端口:- 带自动流量控制功能:是 带IrDA 编码器/解码器:是 带故障启动位检测功能:是 带调制解调器控制功能:是 带CMOS:是 安装类型:表面贴装 封装/外壳:48-TQFP 供应商设备封装:48-TQFP（7x7） 包装:托盘 其它名称:XR16L2551IM-F-ND |
| SC28L194 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Quad UART for 3.3V and 5V supply voltage |
| SC28L194A1A | 功能描述:UART 接口集成电路 3V-5V 4CH UART INTEL/MOT INTRF RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
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