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参数资料
| 型号： | SC403MLTRT |
| 厂商： | Semtech |
| 文件页数： | 20/32页 |
| 文件大小： | 741K |
| 描述： | IC REG DL BCK/LINEAR SYNC 32MLPQ |
| 标准包装： | 1 |
| 系列： | EcoSpeed®, SmartDrive™ |
| 拓扑： | 降压（降压）同步（1），线性（LDO）（1） |
| 功能： | 任何功能 |
| 输出数： | 2 |
| 频率 - 开关： | 1MHz |
| 电压/电流 - 输出 1： | 可调至 0.75V，6A |
| 电压/电流 - 输出 2： | 可调至 0.75V，200mA |
| 带 LED 驱动器： | 无 |
| 带监控器： | 无 |
| 带序列发生器： | 是 |
| 电源电压： | 3 V ~ 28 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 供应商设备封装： | 32-MLPQ（5x5） |
| 包装： | 标准包装 |
| 其它名称： | SC403MLDKR |
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SC403
20
Output Over-Voltage Protection
Over-voltage protection becomes active as soon as the
device is enabled. The threshold is set at 750mV + 20%
(900mV). When V
FB
exceeds the OVP threshold, DL latches
high and the low-side MOSFET is turned on. DL remains
high and the controller remains off, until the EN/PSV input
is toggled or VDD is cycled. There is a 5約 delay built into
the OVP detector to prevent false transitions. PGOOD is
also low after an OVP event.
Output Under-Voltage Protection
When V
FB
falls 25% below its nominal voltage (falls to
562.5mV) for eight consecutive switching cycles, the
switcher is shut off and the DH and DL drives are pulled
low to tri-state the MOSFETs. The controller stays off until
EN/PSV is toggled or VDD is cycled.
VDD UVLO, and POR
UVLO (Under-Voltage Lock-Out) circuitry inhibits switch-
ing and tri-states the DH/DL drivers until V
DD
rises above
3.0V. An internal POR (Power-On Reset) occurs when V
DD
exceeds 3.0V, which resets the fault latch and soft-start
counter to prepare for soft-start. The SC403 then begins a
soft-start cycle. The PWM will shut off if VDD falls below
2.4V.
LDO Regulator
SC403 has an option to bias the switcher by using an inter-
nal LDO from V
IN
. The LDO output is connected to VDD
internally. The output of the LDO is programmable by using
external resistors from the VDD pin to AGND. The feedback
pin (FBL) for the LDO is regulated to 750mV (see Figure 9).
R
LDO1
To FBL pin
VDD
R
LDO2
Figure 9 LDO Voltage Divider
The LDO output voltage is set by the following equation.
2
LDO
1
LDO
R
R
1
mV
750
VLDO
A minimum 0.1糉 capacitor referenced to AGND is
required along with a minimum 1.0糉 capacitor refer-
enced to PGND to filter the gate drive pulses. Refer to the
layout guidelines section for component placement
suggestions.
LDO ENL Functions
The ENL input is used to control the internal LDO. When
ENL is low (grounded), the LDO is off. When ENL is above
the V
IN
UVLO threshold, the LDO is enabled and the
switcher is also enabled if EN/PSV and VDD meet the
thresholds.
The ENL pin also acts as the switcher UVLO (under-voltage
lockout) for the V
IN
supply. The V
IN
UVLO voltage is pro-
grammable via a resistor divider at the VIN, ENL and AGND
pins.
If the ENL pin transitions from high to low within 2 switch-
ing cycles and is less than 1V, then the LDO will turn off
but the switcher remains on. If the ENL goes below the V
IN
UVLO threshold and stays above 1V, then the switcher will
turn off but the LDO remains on. The V
IN
UVLO function
has a typical threshold of 2.6V on the V
IN
rising edge. The
falling edge threshold is 2.4V.
Note that it is possible to operate the switcher with the
LDO disabled, but the ENL pin must be below the logic
low threshold (0.4V maximum). In this case, the UVLO
function for the input voltage cannot be used. The table
below summarizes the function of the ENL and EN pins,
with respect to the rising edge of ENL.
EN
ENL LDO status Switcher status
low low, < 0.4V off
off
high low, < 0.4V off
on
low high, < 2.6V on
off
high high, < 2.6V on
off
low high, > 2.6V on
off
high high, > 2.6V on
on
Applications Information (continued)
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