参数资料
型号: SC4503TSKTRT
厂商: Semtech
文件页数: 8/22页
文件大小: 0K
描述: IC REG BOOST ADJ 1.4A TSOT23-5
标准包装: 1
类型: 升压(升压)
输出类型: 可调式
输出数: 1
输出电压: 可调至 27V
输入电压: 2.5 V ~ 20 V
PWM 型: 电流模式
频率 - 开关: 1.3MHz
电流 - 输出: 1.4A
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: SOT-23-5 细型,TSOT-23-5
包装: 标准包装
供应商设备封装: TSOT-23-5
产品目录页面: 1358 (CN2011-ZH PDF)
其它名称: SC4503TSKDKR
SC4503
POWER MANAGEMENT
Applications Information
Operation
The SC4503 is a 1.3MHz peak current-mode step-up
switching regulator with an integrated 1.4A (minimum)
power transistor. Referring to the block diagram, Figure
2, the clock CLK resets the latch and blanks the power
transistor Q 3 conduction. Q 3 is switched on at the trailing
edge of the clock.
Switch current is sensed with an integrated sense resistor.
The sensed current is summed with the slope-compensat-
ing ramp and fed into the modulating ramp input of the
PWM comparator. The latch is set and Q 3 conduction is
terminated when the modulating ramp intersects the error
clamped by D1 and Q1, follows the voltage at the SHDN SS
pin. The input inductor current, which is in turn controlled
by the error ampli ? er output, also ramps up gradually.
Soft-starting the SC4503 in this manner eliminates high
input current and output overshoot. Under fault condition
(V IN < 2.2V or over-temperature), the soft-start capacitor is
discharged to 1V. When the fault condition disappears, the
converter again undergoes soft-start.
Setting the Output Voltage
An external resistive divider R 1 and R 2 with its center tap
tied to the FB pin (Figure 3) sets the output voltage.
ampli ? er (EA) output. If the switch current exceeds 1.9A (the
typical current-limit), then the current-limit comparator ILIM
will set the latch and turn off Q 3 . Due to separate pulse-
width modulating and current limiting paths, cycle-by-cycle
current limiting is not affected by slope compensation.
=
?
VOUT
(1)
The current-mode switching regulator is a dual-loop feed-
back control system. In the inner current loop the EA output
controls the peak inductor current. In the outer loop, the
error ampli ? er regulates the output voltage. The double
R1
25nA
R2
3
SC4503
FB
reactive poles of the output LC ? lter are reduced to a single
real pole by the inner current loop, allowing the internal loop
compensation network to accommodate a wide range of
input and output voltages.
Applying 0.9V at the SHDN SS pin enables the voltage refer-
ence. The signal “REF NOT READY” does not go low until
Figure 3. R 1 - R 2 Divider Sets the Output Voltage
The input bias current of the error ampli ? er will introduce
an error of:
V IN exceeds its under-voltage lockout threshold (typically
2.2V). Assume that an external resistor is placed between
the IN and the SHDN SS pins during startup. The voltage
?
= ?
?
(
) ?
(2)
? ? ( ) ?
reference is enabled when the SHDNSS voltage rises to
0.9V. Before V IN reaches 2.2V, “REF NOT READY” is high.
Q 2 turns on and the Zener diode Z 1 loosely regulates the
SHDN SS voltage to 1V (above the reference enabling volt-
age). The optional external resistor limits the current drawn
during under-voltage lockout.
When V IN exceeds 2.2V, “REF NOT READY” goes low. Q 2 turns
off, releasing SHDN SS . If an external capacitor is connected
from the SHDN SS pin to the ground, the SHDN SS voltage
will ramp up slowly. The error ampli ? er output, which is
The percentage error of a V OUT = 5V converter with R 1 =
100k ? and R 2 = 301k ? is
= ? = ?
This error is much less than the ratio tolerance resulting
from the use of 1% resistors in the divider string.
? 2007 Semtech Corp.
8
www.semtech.com
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