参数资料
型号: SC4524BSETRT
厂商: Semtech
文件页数: 14/18页
文件大小: 0K
描述: IC REG BUCK 2A 8SOIC
产品培训模块: Power Supplies 101
标准包装: 1
类型: 降压(降压)
输出数: 1
输入电压: 3 V ~ 18 V
PWM 型: 电流模式
频率 - 开关: 300kHz ~ 1.3MHz
电流 - 输出: 2A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm Width)裸露焊盘
包装: 标准包装
供应商设备封装: 8-SOIC-EP
产品目录页面: 1358 (CN2011-ZH PDF)
其它名称: SC4524BSEDKR
2 π ?  6 ?  0 ? 22 .   ?  0 3
C 5 =
 
3
= 0 . 45 nF
SC4524B
C 8 =
 
2 π ? 600 ?  0 3 ? 22 .   ?  0 3
=  2 pF
V o G PWM (   + s R ESR C O )
(3) Place the compensator zero, F Z  , 2 between  0% and
V c (   + s / ω p ) (   + s / ω n Q + s / ω n )
F Z . R  
(5) Then, the parameters of the compensation network R
G CA ? R S
G PWM ≈ , ω p ≈ , ω Z =
 0 20
R 7 =
  should be minimized. Since the power switch is already
,
ESR C O
ApplicationsInformation(Cont.)
=
20% of the crossover frequency, F C .
(4) Use the compensator pole, F P  , to cancel the ESR zero,
R C O
can be calculated by
A C
g m
capacitor, the main power switch and the freewheeling
diode carry pulse current (Figure 9). For jitter-free
operation, the size of the loop formed by these components
integrated within the SC4524B, connecting the anode of
the freewheeling diode close to the negative terminal of
the input bypass capacitor minimizes size of the switched
current loop. The input bypass capacitor should be placed
close to the IN pin. Shortening the traces of the SW and
C 5 =
C 8 =
 
2 π F Z   R 7
 
2 π F P   R 7
BST nodes reduces the parasitic trace inductance at these
nodes. This not only reduces EMI but also decreases
switching voltage spikes at these nodes.
The exposed pad should be soldered to a large ground
where g m =0.28mA/V is the EA gain of the SC4524B.
Example : Determine the voltage compensator for an
plane as the ground copper acts as a heat sink for the
device. To ensure proper adhesion to the ground plane,
avoid using vias directly under the device.
800kHz,  2V to 3.3V/2A converter with 22uF ceramic
output capacitor.
V IN
Choose a loop gain crossover frequency of 80kHz, and
(20% of F = C ), ? ? ? 20   ? log P  ? ?   =600kHz. 2 π From Equation (9), the
? FB ? ?
and F G R V FB ? ? ?
place voltage compensator zero and pole at F Z  = 6kHz
F C C O
V O ?
required compensator F C gain V at ? ? F C is
A C = ? 20 ? log ? ? ? CA ? S
A C
? G CA R S 2 π C O O
V OUT
A C = ? A C ? = log ? ? ? 20 ? log ? ? 3 ?
?
  ?       . 0 ?  
? 28 ? 6 .   ?  0 28 2 ? π 6 ? .   ? ?  0 3 ? ? 3 22 2  0 ? ? 6 80 3 . ? 3  0 3 ? 22 ?  0 ? 6
? π
?
? =  5 . 9 dB
20 ? ? =  5 . 9 dB
80  0 ?
?
  . 0 ?
3 . 3 ?
Z L
R 7 =
= 22  5 . 3 . 9 k
R 7 =
= 22 . 3 k
0 . 28 ?  0 ? 3 3 = 0 . 45 nF
C 5 =
2 π ?  6 ?  0 ? 22 .   ?  0
C 5 =
= 0 . 45 nF
 
C 8 =
2 ?  0 π 3 ?  6 . ?    0  0 3 3 ? = 22 . pF ?  0 3
 2
C 8 = G
=  2 pF
?  0 3
2 π ? 600 ?  0 ? 22 .  
V o PWM (   + s R ESR C O ) 3
 5 . 9
Then the compensator parameters are
 0 20
0 . 28 ?  0 ? 3  0 20
 
3
 
2 π ? 600 ? 22 ?  
 
=
2
V c (   + s / ω p ) (   + s / ω n Q + s 2 / ω n )
Select R 7 =22. k, C 5 =0.47nF, and C 8 = 0pF for the design.
Figure 9. Heavy lines indicate the critical pulse
current loop. The inductance of this
loop should be minimized.
G PWM ≈ (     + , s R ESR C O ω ) Z =
G PWM ≈ V o
ω p
,
,
Compensator parameters C for various 2 typical applications
V c (   + s / ω p ) (   + s / ω n Q + s / ω n )
upon request for detailed calculation of the compensator
 0
R 7 =
parameters.
R
 
 
G PWM ≈ , ω p ≈ , ω Z =
G CA ? R S
R C O
R ESR C O
2 π F Z   R 7
C 8 =
 
2 π F P   R 7  0 20
In a step-down switching regulator, the input bypass
C 5 =
R  
A C
are listed in Table 4. A MathCAD program is also available
20
g m
C 5 =
PCB Layout Considerations
A C
g m
 
2 π F R
,
Vin
+
 4
Cu
相关PDF资料
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SC4524CSETRT IC REG BUCK ADJ 2A 8SOIC
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