参数资料
| 型号： | SC4524DSETRT |
| 厂商： | Semtech |
| 文件页数： | 13/22页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK ADJ 2A 8SOIC |
| 标准包装： | 1 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 1 V ~ 17.28 V |
| 输入电压： | 3 V ~ 18 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 300kHz ~ 1.3MHz |
| 电流 - 输出： | 2A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm Width）裸露焊盘 |
| 包装： | 标准包装 |
| 供应商设备封装： | 8-SOIC-EP |
| 其它名称： | SC4524DSEDKR |
Fig.7
SC4524D
Applications Information (Cont.)
Minimum Soft-start Capacitance CSS
To ensure normal operation, the minimum soft-start
capacitance C SS can be calculated in terms of the output
capacitance C O and output load current I O according to
the following equations.
Loop Compensation
The goal of compensation is to shape the frequency
response of the converter so as to achieve high DC
accuracy and fast transient response while maintaining
loop stability.
C O N T RO LLE R A N D S C H O TT K Y D IO D E
REF
+
CA
Rs
Io
Substituting the first equation into the second equation,
FB
-
EA
Vc
V ram p
PW M
M O D U LATO R
SW
L1
Vo
C5
COMP
Co
R4
where V SS is the soft-start capacitor voltage and I SS is the
soft-start charging current. V 1 is the voltage defined in
Figure 2.
R7
C8
R esr
R6
R R 4 4 = = R R 6 6 ? ? ? 1 . 0 O V ? ? 1 1 ? ? ?
Substituting the = = third V O equation of this section into the
D V O + V D
V V IN + + V D D ? ? V V CESAT
previous equation, IN
( ( V V O O + + V V D D ) ) ? ? ( ( 1 1 ? ? D ) )
D D I I L L = =
( ( V V O O + + V V D D ) ) ? ? ( ( 1 1 ? ? D ) )
L L 1 1 = =
20 % ? ? I I O O ? ? F F SW
The block = = diagram log ? ? ? Figure 7 ? ? shows the ? ? control loops of a
? ? 20 ? ? log G R
A A C C
? 1 1 V FB ?
V V O O ? ? ?
? G CA R S S 2 2 π π F F C C C C O O
? the SC4524D. The inner loop (current
buck converter with
1 1
1 1
loop) consists of a current sensing resistor (R s =5.5m W ) and
? ? 20 ? ? log ? ? ?
a current C = = amplifier log (CA) with gain (G ? ? CA =18.5). The outer
A A C
20
? ? 3 3
80 10 3 22
loop (voltage loop) consists . . 1 1 of ? ? 10 error π π amplifier (EA), ? ? 10 ? 6
? ? 28 ? ? 6 6
2 2 ? ? 80 ? ? 10 3 ? ? 22 a 10
28
10
an
10 15 20 . 9
R 7 =
22 . 3 k
? 3 = 22 . 3 k
R 7
C C 5 5 = =
= = 0 0 . . 45 nF
compensator (C 5 , R 7 , and C 8 ).
3 3 ? 22 . 1 ? 10 3 3
2 2 π π ? ? 16 ? ? 10 ? 22 . 1 ? 10
1 1
inductance L 1 , output capacitance C O and loading R, the
2 2 to output (V 3 O ) transfer function in Figure 7 is
control (V C )
? ? 3 .
To ensure successful startup, the total current drawn
from the output must be less than the maximum output
capability of the part,
? V O ?
? 1 . 0 V ?
D
CESAT
D
F SW ? L 1
Rearranging,
D
20 % SW
Figure 7 — Block diagram of control loops
20 in ?
CA
?
PWM modulator, and a LC filter.
15 . 9
= 10 20 =
Since the current loop is internally closed, the remaining
. . 28 28 10 ? 3
task for the 0 loop ? compensation is to design the voltage
45 nF
16 10
For a converter with switching frequency F SW , output
π ? 600 ? 10 3 ? 22 . 1 ? 10 3
given by:
? 6
1 1 . . 0 0
3 . 3
I I RMS _ _ CIN = = I I O O ? ? D ? ? ( ( 1 1 ? ? D ) )
= ( 1 + s / ω PWM () 1 + s / ω ESR Q + O s 2 2 / ω 2 2 )
RMS CIN D D
V o = G PWM ( 1 + s R ESR C O )
V c ( 1 + s / ω p ) ( 1 + s / ω n Q + s / ω n )
This transfer function has a finite DC gain
capacitance and V the D load ? ? ? ESR +
current. Larger C SS ? ? ? is necessary
D D V O O = = D I I L L ? ? ? ? ESR + 8 ? F
1 1
when starting into a heavy load (small R). C C O O ? ? ?
8 ? F SW ? ?
? ?
C C IN IN > > 4 ? D V O ? F
G PWM ≈ ≈ G ? R , ,
R R
A C
R 7 = = 10
g g m
C C 5 5 = = 2 π F R
ω p p ≈ ≈ R C , ,
ω Z Z = = R
Therefore the minimum C SS depends on the output
?
SW
I I O
4 ? D V IN ? F SW
G PWM
R 7
G CA ? R S
A
10 20 20 C
m
1 1
2 π F Z Z 1 1 R 7 7
ω 1
R C O O
ω 1
R ESR C O
13
, ,
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