参数资料
| 型号： | SC4524DSETRT |
| 厂商： | Semtech |
| 文件页数： | 14/22页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK ADJ 2A 8SOIC |
| 标准包装： | 1 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 1 V ~ 17.28 V |
| 输入电压： | 3 V ~ 18 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 300kHz ~ 1.3MHz |
| 电流 - 输出： | 2A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm Width）裸露焊盘 |
| 包装： | 标准包装 |
| 供应商设备封装： | 8-SOIC-EP |
| 其它名称： | SC4524DSEDKR |
0 20
? 10 12 3 pF
=
1
16 ? 10 ? 22 . 1 ? 10 3
3
15 . 9
? = 22 . 3 k
3
= 0 . 45 nF
SC4524D
= 12 Information (Cont.)
Applications pF
600 / ω ? 10 ) 3
? 22 . 1 ? 10 3
1
2 2
n
1 G PWM ( 1 + s R ESR C O ) 1
R / C ω O p ) ( 1 + s / ω n Q + s R 2 ESR ω C n 2 O )
anESRzeroF Z at
, ω Z =
/
,
(2) Select the open loop crossover frequency, F C , between
10% and 20% of the switching frequency. At F C , find the
required compensator gain, A C . In typical applications with
ceramic output capacitors, the ESR zero is neglected and
a dominant low-frequency pole F P at
the required compensator gain at F C can be estimated by
ω p ≈
ω Z =
,
,
A C = ? 20 ? log ? ?
?
? FB ? ?
R
A ? R S
,
1 1
R C O R ESR C O
and double poles at half the switching frequency.
? 1 1
? G CA R S 2 π F C C O
V ?
V O ?
10 20
R 7 =
C 5 =
1 R 7
1
1 R 7
Including the voltage divider (R 4 and R 6 ), the control to
feedback transfer function is found and plotted in Figure
8 as the converter gain.
Since the converter gain has only one dominant pole at
low frequency, a simple Type-2 compensation network
is sufficient for voltage loop compensation. As shown in
Figure 8, the voltage compensator has a low frequency
integrator pole, a zero at F Z1 , and a high frequency pole
at F P1 . The integrator is used to boost the gain at low
frequency. The zero is introduced to compensate the
excessive phase lag at the loop gain crossover due to the
(3) Place the compensator zero, F Z1 , between 10% and
20% of the crossover frequency, F C .
(4) Use the compensator pole, F P1 , to cancel the ESR zero,
F Z .
(5) Then, the parameters of the compensation network
can be calculated by
A C
g m
1
2 π F Z 1 R 7
integrator pole (-90deg) and the dominant pole (-90deg).
The high frequency pole nulls the ESR zero and attenuates
high frequency noise.
C 8 =
1
2 π F P 1 R 7
60
where g m =0.3mA/V is the EA gain of the SC4524D.
MP
EN
SA
Fc
OP
CO
NV
AIN
ER
T ER
GA
A C = ? 20 ? log ? ?
1 1 1 . 0 ?
? 18.5 ? 5 . 5 ? 10 ? 3 2 π ? 80 ? 10 3 ? 22 ? 10 ? 6 3 . 3 ?
30
0
-30
-60
1K
Fp
10K 100K 1M
Fz1 Fp1
LO
IN
Fz Fsw/2
FREQUENCY (Hz)
CO
G
TO
RG
AIN
10M
Example : Determine the voltage compensator for an
800kHz, 12V to 3.3V/2A converter with 22uF ceramic
output capacitor.
Choose a loop gain crossover frequency of 80kHz, and
place voltage compensator zero and pole at F Z1 =16kHz
(20% of F C ), and F P1 =600kHz. From the equation in step (2),
the required compensator gain at F C is
? ? ? = 11 . 4 dB
Figure 8 — Bode plots for voltage loop design
Therefore, the procedure of the voltage loop design for
the SC4524D can be summarized as:
(1) Plot the converter gain, i.e. control to feedback transfer
function.
14
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